The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An efficient compact implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves low level in hardware resources, so it is efficient for area constraints applications such as smart cards. The proposed implementation reaches a data throughput of 29.7 Mbps at 111 MHz clock frequency. The design was coded using VHDL language and for the hardware implementation,...
High-speed hardware for Keccak, which was selected as a new standard hash function named SHA-3, was developed and its performance was evaluated against SHA-1 and −2 circuits through the use of various FPGA platforms. The results showed that Keccak is suitable for high-speed hardware implementations, but it is getting harder to implement on new FPGA devices, due to the current trends in architecture...
This paper presents two high performance FPGA architectures for the 2D DCT computation for Ultra High Definition video coding systems. Both architectures use Distributed Arithmetic to perform the necessary multiplications instead of traditional multipliers. The first architecture uses 105 clock cycles to transform an 8×8 block and reaches a rate of up to 206 samples per second at a 338.5 MHz frequency,...
An FPGA implementation of the 128-bit SEED block cipher is presented in this paper. The proposed architecture achieves high-speed with little hardware resources using feedback logic and inner pipeline with negative edge-triggered registers. In this way, the delay of the critical path is reduced, without increasing the latency of cipher execution. The proposed implementation reaches a data throughput...
AES-GCM(Advanced Encryption Standard with Galois Counter Mode) is an encryption authentication algorithm, which includes two main components: an AES engine and Ghash module. Because of the computation feedback in Ghash operation, the Ghash module limits the performance of the whole AES-GCM system. In this study, an efficient architecture of Ghash is presented. The architecture uses an optimized bit-parallel...
Impulse noise removal is a very important preprocessing operation in many computer vision applications. This paper presents a noise removal approach based on a simple conditional technique. As evaluations show, the presented technique performs significantly better than standard median filter and achieves superior image quality. Experimental FPGA implementation of the proposed technique for window...
This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width, which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating...
Decimal floating point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of FPGAs. Our multiplier is based on BCD recoding schemes, fast...
Convolutional codes are one of the Forward Error Correction (FEC) codes that are used in every robust digital communication system. Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. Software Defined Radio (SDR) is realized using highly configurable hardware platforms. Field Programmable Gate Array...
This paper describes the algorithm and design tradeoffs for multiple hardware implementations of parallel high-radix scalable Montgomery multipliers. Hardware implementations of Montgomery multipliers require choosing a radix, shift direction, and whether to use Booth encoding. Presented are processing element designs exploring combinations of radices 2, 4, and 8, right vs. left shifting, and Booth...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.