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In this paper, we describe an FPGA system for the real-time processing of Poisson image Editing. Poisson Image Editing is a powerful method to overlay an image on another image seamlessly. In this method, however, a simple equation is repeatedly applied to each pixel, and this repetition makes its computational complexity very high. In our system, a very deep pipeline is used to apply the equation...
Undergraduate students rapidly implement a partially-reconfigured, real-time video processor on the Xilinx PYNQ board. The video processor performs various real-time operations including Sobel edge detection, embossing, averaging, an interactive Pong game, etc., using a separate partially-reconfigurable bit-stream for each distinct function. Selection of image-processing functions is accomplished...
This paper presents the authors' research work in the fields of embedded real-time softcore systems on FPGAs and specialized optimizing assembly language compiler. With this softcore processor, we are targeting a highly specialized field of applications that require a large floating point precision and other unique characteristics. Therefore, a specialized optimizing assembly language compiler is...
The previous studies of real-time imaging process using directly delay calculation design on FPGA, because the limited number of memory on chip. In this paper, to achieve higher frequency, a look-up table which carries the distance information has been introduced in. As the operation frequency of memory on Field-programmable gate array (FPGA) can reach to as high as 400MHz, which is much higher than...
In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture...
We present a FPGA implementation of a pedestrian detector that can process VGA video at a frame rate of 30–40 frames per second in real time. The architecture implements an offline trained boosted detector in an attentional cascade. The cascade evaluates each frame using histogram of gradient (HOG) features in the LUV color space. Pedestrian targets are identified at 27 scales. Feature aggregation...
Edge Detection is one of the basic characteristics of the image. It is an important basis for the field of image analysis such as image segmentation, target area identification, extraction and other regional forms. The edge detection operators such as canny, sobel, prewitt operators detects the wide range of edges in image. These operators apply the convolution operation at each pixel to have gradient...
Loss less compression is often used before writing data to a storage medium or transmitting across a transmission medium. Compression aids by saving storage space or transmission bandwidth, a decompression operation is performed when the data is subsequently read. Though this scheme has clear benefits, the execution time of compression and decompression is critical to its application in real-time...
Reconfigurable hardware such as FPGAs are being increasingly employed for accelerating compute-intensive applications. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues with scalability and compatibility. We present SHARC - Streaming Hardware Accelerator with Run-time Configurability, for an FPGA-based...
To transfer functionalities from software to dedicated hardware is necessary when the performance of the available DSP processor can not achieve the required constraints. The hardware implementations of pipeline-folding 64-Tap filter modules used in a heavy ion accelerator for real-time digital signal processing are described in this paper. Pipeline-folding mechanism is applied to the hardware designs...
In this paper, we propose a real-time and adaptive method for labeling and recognition of multiple infrared markers. A single-frame based iteration process is developed to obtain the suitable threshold. A sliding window is proposed to propagate the preliminary labels and to reduce the capacity of equivalent tables handling. The labeling and recognition are realized by merging the results of domains...
High-speed data acquisition system is designed with the FPGA device EP2S180 as controlling unit. In order to heighten data acquisition speed, four pipelined architecture high-speed AD devices is adopt acted on the state machine and phase delay clock which is designed based on FPGA device. The conversion storage data in the coach composed of block RAM in the EP2S180 is transferred to main memory by...
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