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The design and optimization of data-centers-on-a-chip (DCoC) requires accurate mathematical modeling of the workloads. We describe a statistical physics-inspired formalism that allows both the derivation of state space representation of the network and the dynamic optimization.
Deadlock is a common problem in 3D networks-on-chip. In this paper, we propose a lightweight and deadlock-free turn-guided routing scheme named TURO without requiring any virtual channels, which is a minimal routing guided by a new 3D turn model NeoOE. The theoretical analysis and experimental results show that TURO possesses improved adaptivity, higher performance and lower overhead compared with...
In a Multi-Processor System-on-Chip (MPSoC)-based embedded system with Network-on-chip (NoC) as the communication architecture, routing of the communication traffic among the Processing Elements (PEs) contributes significantly to the overall latency, throughput and energy consumption. Design of an efficient routing algorithm for NoC requires a thorough understanding of the role of individual components...
3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with short vertical ones. Achieving higher performance along with reducing the network latency can be obtained by utilizing an efficient communication protocol in 3D Networks-on-Chip (NoCs). In this work, several unicast/multicast partitioning methods are explained in order to find an advantageous...
Networks-on-chip (NoCs) have been proposed as a scalable solution to solving the communication problem in multicore systems. Although the queuing-based approaches have been traditionally used for performance analysis purposes, they cannot properly account for many of the traffic characteristics (e.g., non-stationary, self-similarity, higher order statistics) that are crucial for multicore platform...
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors, increasing the need for accurate and efficient modeling to aid the design of these highly-integrated systems. Towards this modeling goal, we present a methodology for packet-level static timing analysis in NoCs. Our methodology enables quick and accurate gauging of the performance parameters of a virtual-channel...
Reliability evaluation based on analytical models is a precise method for dependability analysis before and after designing the fault-tolerant systems. In this paper, we present the precise formulations for the inherent reliability of mesh-based NoCs that also depend on the employed routing algorithm and traffic model. Based on this analysis, the effects of some permanent failures in the links, switches...
Future system-on-chip (SoC) designs will need efficient on-chip communication architectures that can provide efficient and scalable data transport among the intellectual properties (IPs). Designing and optimizing SoCs is an increasingly difficult task due to the size and complexity of the SoC design space, high cost of detailed simulation, and several constraints that the design must satisfy. For...
Network-on-chip (NoC) architectures employing packet-based communication are being increasingly adopted in system-on-chip (SoC) designs. In addition to providing high performance, the fault-tolerance and reliability of these networks is becoming a critical issue due to several artifacts of deep sub-micron technologies. Consequently, it is important for a designer to have access to fast methods for...
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