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This paper presents a fast switching frequency synthesizer for a Mode-1 MB-OFDM UWB system. The proposed architecture with a new frequency plan is designed to simplify the synthesizer implementation for optimizing the system power consumption and sideband rejection ratio. This frequency generator consists of a single phase-lock-loop (PLL), a 12-phase coupled ring oscillator, tri-mode divider-by-2...
A 9 b 100 MS/s successive approximation register (SAR) ADC has been implemented in 65 nm CMOS, with an active area of 0.012 mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1 dB (8.53 ENOB) and consumes 1.46 mW from a 1.2 V...
Multiple antennas system is used to replace traditional single antenna circuitry in radio transceiver system in order to improve transmission capability and reliability. With multiple antennas, data transfer rate can be increased by a factor of n, where n is the number of antennas used in the transceiver. To avoid the uses of multiple RF chain associated with the multiple antennas, an antenna selection...
This paper presents an LC-tuned, 24-GHz single-pole double-throw (SPDT) transmit/receive (T/R) switch implemented in 90-nm CMOS. The design focuses on the techniques to increase the power handling capability in the transmit (Tx) mode under 1.2-V operation. The switch achieves a measured P-1dB of 28.7 dBm, which represents the highest linearity, reported to date, for CMOS millimeter-wave T/R switches...
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