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A track-and-hold amplifier using 65 nm CMOS process is presented in this paper. The cascode topology with inductive peaking technique is employed to enhance voltage headroom and bandwidth. The input parasitic capacitance of the output buffer is designed as the hold-mode element to further reduce chip size. The dc supply voltage is 1.8 V with a total power consumption of 197 mW. When the input frequency...
This paper describes a new switching topology of a sampling mixer for SAW-less GPS (L1 band) receivers. The GPS receiver with the new mixer achieved NF 2.5dB and good blocking performance. In an alternative implementation, the mixer is stacked under a Quadrature VCO to reuse supply current. As a result, the current consumption of the GPS receiver is 11mA from 1.8V supply while maintaining blocking...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
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