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A 9μW 88dB DR switched-opamp (SO) ΔΣ modulator is implemented in a low cost 0.35μm CMOS process. To evaluate the effects of finite voltage gain and 1/f noise clearly, two high efficient methods are introduced. And a new fully switched-off SO with a 50% power saving and double Figure-of-Merit (FOM) over the traditional type is proposed to reduce the total power. Besides, to improve the performance,...
A novel low dropout regulator (LDO) is proposed in this paper which has high power supply rejection ratio (PSRR) in a wide frequency range and its transient response performance is also improved. In order to get good performance on PSRR, a full differential folded cascode structure error amplifier is used, which also increases the precision of the proposed LDO. A transient enhancement circuit unit...
This paper presents the development of a low-power rail-to-rail SAR-ADC to be used in a medical implants. The first part discusses the principle schematic and the requirements for the neuronal implant application. Additionally, a full description of each part of this ADC SAR will be given. And finally the last part presents measurement results of a fabricated test chip in 0.35μM CMOS technology, with...
The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to the calibration. We present a 14 bit DAC, designed in a CMOS 0.35 μm process and based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. This DAC features an INL lower than 0.5 LSB at 5 MHz, and dissipates less than 7 mW.
There is a growing demand for low-noise, small-size and programmable biopotential acquisition systems. A crucial circuit block is the high-gain amplifier which also constitutes the interface to the patient. We propose a low-power and low-noise front-end with configurable gain for recording of signals such as the electroneurogram (ENG) or electromyogram (EMG). The proposed circuit consists of an input...
This paper presents a low-power and self-biased neural amplifier for implantable EEG recording system ICs with a high-density interface. To achieve low-power consumption, small die-area, high gain, and high CMRR, a fully differential Chappell OTA is employed along with a capacitive feedback loop. The amplifier operating at ±1.2V has a gain of 65.6dB and consumes a power of 1.7μW. The bandwidth extends...
A multi-function two-stage chopper-stabilized preamplifier (PAMP) for MEMS capacitive microphones (MCM) is presented. The PAMP integrates digitally controllable gain, high-pass filtering and offset control, adding flexibility to the front-end readout of MCMs. The first stage of the PAMP consists of a source-follower (SF) while the second-stage is a capacitive gain stage. The second-stage employs chopper-stabilization...
We present the first CMOS-only receiver chip for NMR-applications at 300 MHz. The system consists of an on-chip reception coil, a tuning-capacitor, a downconversion-mixer and a low-frequency gain-stage as well as biasing and offset-compensation circuitry. It has an input referred voltage noise density of 0.7 nV/radicHz and a gain of 75 dB. The power consumption is 18 mA from a single 3.3 V supply...
We present a fully differential 128-channel integrated neural interface. It consists of an array of 8times16 low-power low-noise signal recording and generation channels for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with a programmable gain of 54 dB to 73 dB, and a fully differential 8-bit column-parallel...
A fully-integrated high-pass CMOS filter with Hertz/sub-Hertz break frequencies is presented. The new common-mode voltage is set by a simple feedback loop comprising a servo-amplifier and two common-drain transistors. No bulky resistors are required, making the approach compact and fully integrated. Since the input current is limited to tens of pA, the filter equivalent input-resistance reaches GOmega-range,...
This paper presents a high performance readout circuit for Infrared detector. The circuit is composed of capacitor trans-impedance amplifier (CTIA) and correlation double sampling (CDS) circuit. The CTIA structure is used to convert the photo-current into voltage, and could obviously improve the readout accuracy of weak current signal. And the CDS structure is used to reduce the fixed pattern noise...
This paper describes a design of a switched capacitor common mode feedback (SC CMFB) folded cascode operational transconductance amplifier for low power and high-speed sigma-delta modulators. An algorithmic driven methodology is developed ending to the optimal transistor geometries. Using a 0.35 mum CMOS process, the OTA circuit has been designed to achieve 82.94 dB DC gain, 526 MHz unity-gain frequency,...
We present a capacitive digital-to-analog converter (DAC) architecture combining properties of the binary-weighted and serial charge-redistribution DACs to yield high integration density and high accuracy. The architecture provides the flexibility to trade area with conversion speed based on a set of area-speed-linearity constraints. We validate the architecture using a 10-bit two-step DAC example,...
A 40 MSample/s, 10-bit, 3.3V pipeline ADC is presented. In order to achieve very low power consumption, it employs a high bandwidth low-power amplifiers technique and a low power low offset dynamic comparators technique. The ADC is designed in 0.35 mum CMOS technology and occupies 1.2*0.8 mm2.
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
An integrated readout circuit for Lab-on-a-Chip applications is presented. The overall system consist of a 640times480 array of capacitor sensors and actuators. Sensors detect dielectric permittivity variation thanks to dielectrophoresis (DEP) process. Usually for this kind of applications an off-chip analog-to-digital converter is used. As a consequence, the noise floor increases and high signal-to-noise...
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