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A programmable gain amplifier (PGA) with DC offset cancellation (DCOC) is designed by 0.18 μm CMOS process in this paper. The PGA adopts two-stage in cascade based on a novel feedback structure, which realizes a constant 3-dB gain step and avoids using multiplexing decoder. The proposed DCOC function block features an adequately low cut-off frequency and completes the challenge of integration on chip...
A new CMOS readout circuit with non-uniformity calibration for diode uncooled infrared focal plane array (IRFPA) is presented in this paper. A new transconductance amplifier with offset cancellation structure is proposed, utilizing output offset voltage storage. The bias current of each pixel is adjusted by a current splitting DAC array, calibrating the mismatch of the current sources and the non-uniformity...
Hardware Trojan, similar to the computer viruses, is a new threat in modern System-On-Chips (SOCs) such as security chips and trusted computer systems. Despite the risks that such an attack entails, little attention has been given to the methods of run-time Trojan detection. In this paper, the defects in existing security chips are analyzed and an improved bus architecture for hardware Trojan protection...
This paper presents a high performance readout circuit for Infrared detector. The circuit is composed of capacitor trans-impedance amplifier (CTIA) and correlation double sampling (CDS) circuit. The CTIA structure is used to convert the photo-current into voltage, and could obviously improve the readout accuracy of weak current signal. And the CDS structure is used to reduce the fixed pattern noise...
A multi-stage digital decimator for sigma-delta analog-to-digital converter with an oversampling ratio of 64 is described. To optimize the architecture of the digital filters and the circuit implementation, multi-rate multi-stage decimation, half-band filter and multiplier sharing are used. The filter is designed and simulated using SIMULINK and MATLAB while the hardware realization is obtained using...
A multibeam satellite system with on-board processing and memory is studied here. In this system, multiple slotted ALOHA up-links carry the traffic from spatially disjoint earth zones to the satellite. Packets are accepted at the satellite if memory is available and are routed to their destination zones. The model considered here will allow more than one transponder to serve a destination zone...
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