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The average smart phone user picks up the device 1,500 times a week. Wireless communication appears to be taking over our lives but it also presents interesting challenges to RF designers. This paper contends that the mobile terminal will emerge as a central command post for most of our daily affairs and will therefore sustain an increasingly heavier load in terms of speed, power dissipation, and...
In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm...
Harmonic-reject mixers are required in receivers to prevent signals near the LO harmonics from introducing large interferences into the desired signal band. To achieve high attenuation of interferers in harmonic-reject mixers, sub-mixings with accurate gain are required. Existing oversampling harmonic-reject mixer structures employ either three or four mixers with different gains. A harmonic-reject...
Repeaterless low swing interconnects are potential candidates for high speed low power signaling over on-chip global wires. Capacitive pre-emphasis at the transmitter has been shown to improve the achievable data rate by increasing the relative power at high frequencies. This paper shows an improved transmitter with a 1-tap feed-forward equalizer in addition to capacitive pre-emphasis. A design method...
In this paper, a sample-and-hold circuit for a reconfigurable ADC is presented. This design is based on TSMC 0.18µm process. Flip-around architecture is employed to implement overall circuit which may contribute to low noise and fast settling with consuming lower power. To achieve high linearity, improved bootstrapped switches are introduced in this design. A fully differential folded-cascode OTA...
This paper presents a 60GHz heterodyne receiver architecture with IF sub-sampling. A particular arrangement of the frequency plan allows anti-alias filtering by the charge-domain subsampler. Down-conversion, channel filtering and IQ demodulation are merged into a unique operator without any extra cost in terms of area and power consumption. The proposed architecture is able to receive up to 4 bonded...
The constant demand for wireless systems pushes engineers and researchers to develop more innovative systems to improve performance. Remarkable improvements have been recently realized on charge-domain SAR ADCs to reach the speed of a few tens of MS/s with medium resolution and low power consumption [1,2]. This has shifted the power bottleneck to the preceding block in a wireless receiver, conventionally...
These tutorials discuss the following: Integrated LC oscillators; Embedded Memories for SoC: Overview of Design, Test, and Applications and Challenges in the Nano-Scale CMOS; Ultra Low-Power and Low-Voltage Digital-Circuit Design Techniques; Layout - The Other Half of Nanometer Analog Design; DPLL-Based Clock and Data Recovery; Practical Power-Delay Design Trade-offs; Distortion in Cellular Receivers;...
An analog baseband chain for a Synthetic Aperture Radar (SAR) receiver implemented in a 130nm CMOS technology is presented in this paper. Occupying 0.23mm2 of silicon area, the baseband chain consists of a three-stage Variable Gain Amplifier (VGA), a 5th-order gm-C Low Pass Filter (LPF) and an Output Buffer (OBUF). The gain of the chain can be controlled by tuning the control voltages of the VGA and...
In this paper, the optimized matching circuit between RF SAW (surface acoustic wave) filter output and RF LNA (low noise amplifier) input on the limited PCB (Print Circuit Board) placement space has been gotten by simulation. With the matching circuit, the conducted sensitivity of receiver of the GSM mobile phone is about -109 dBm. Such good sensitivity can decrease desense (sensitivity degradation)...
A low-voltage 5th-order continuous-time ΣΔ modulator for a universal mobile TV receiver is presented. A unique feature of the proposed modulator is the blocker filtering provided using a 3rd order notch filter employing frequency dependent negative resistance (FDNR). The noise added by the FDNR is shaped. The modulator employs 3-level switched-capacitor DAC in the feedback. It has been implemented...
A 6th order Chebyshev type I low pass filter applied in zero-IF wireless receivers, implemented in 0.18 ??m CMOS technology is introduced, this filter is realized with leapfrog structure, has an attenuation of 30 dB at 5.25 MHz, less than 1 dB in-band ripple, 25 nV/sqrt(Hz) input referred noise at 5 kHz, and draws 2.6 mA from 1.8 V supply. By employing frequency calibration circuit, the cut-off frequency...
We present the first CMOS-only receiver chip for NMR-applications at 300 MHz. The system consists of an on-chip reception coil, a tuning-capacitor, a downconversion-mixer and a low-frequency gain-stage as well as biasing and offset-compensation circuitry. It has an input referred voltage noise density of 0.7 nV/radicHz and a gain of 75 dB. The power consumption is 18 mA from a single 3.3 V supply...
A 1Gs/s CMOS track-and-hold for the upcoming generation of Ethernet applications (10GBASE-T) is presented. The Track-and-Hold is designed to be employed as front-end in a time-interleaved analog-to-digital converter and it is based on an open-loop architecture composed of an input buffer and a highspeed switch. The proposed Track-and-Hold, designed in a 65 nm low-power CMOS process, exhibits a total...
A frequency translation technique exploiting properties of the current-driven passive mixers is presented to implement built-in out-of-band blocker filtering, intended for FDD applications such as 3G. The mathematical findings enable us to optimally size the components for maximal RF front-end gain and minimal noise figure. A prototype zero-IF receiver is fabricated in 65nm CMOS, and achieves a NF...
The low noise amplifier is the key part for front-end device of the receiver in the GPS. A 1.8 V 0.18 mum CMOS LNA for GPS applications has been designed. Two kinds of low noise amplifier (LNA) for single-end cascade structure and differential cascade structure respectively are presented in this paper. Cadence software is used to optimize the two circuits. It provides a series of good results in Noise...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
This paper presents a 4th-order Chebyshev HPF in 65 nm CMOS process with programmable gain and corner frequency to support ADSL and 5/6 band VDSL applications. The HPF improves noise performance by applying capacitive feedback and feedforward in the filter. It achieves a 70 dB MTPR and -161 dBm/Hz (2.8 nV/radicHz) input referred noise for ADSL mode. An IM3 of -80 dBc at 10 MHz is measured for VDSL...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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