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Deterministic replay, which provides the ability to travel backward in time and reconstruct the past execution flow of a multiprocessor system, has many prominent applications. Prior research in this area can be classified into two categories: hardware-only schemes and software-only schemes. While hardware-only schemes deliver high performance, they require significant modifications to the existing...
Many-core systems are increasingly popular in embedded systems due to their high-performance and flexibility to execute different workloads. These many-core systems provide a rich processing fabric but lack the flexibility to accelerate critical operations with dedicated hardware cores. Modern Field Programmable Gate-Arrays (FPGAs) evolved to more than reconfigurable devices, providing embedded hard-core...
Many-core architectures are similar to a computer network, where it is necessary to ensure the security during the execution of sensitive applications. This article discusses two security-related issues: the secure admission of applications and the prevention of resource sharing during their execution. The safe application admission is an open research subject for many-core systems. Although several...
Many multicore and manycore architectures support hardware cache coherence. However, most of them rely on software techniques to maintain Translation Lookaside Buffer (TLB) coherence, namely the TLB shootdown routine, which is a costly procedure, known to be hardly scalable.The TSAR architecture is a manycore architecture including hardware TLB coherence, but in which the TLB coherence mechanism is...
In embedded SoC applications, the demand for integration of heterogeneous processors on a single chip is increasing. On-chip heterogeneity allows different processors to employ different cache coherence protocols which in turn add difficulties in the task of integrating different coherence protocols as well as realizing the task of coherence verification. This work first proposes an efficient mechanism...
Shared memory resources are inevitable components in modern SOC architecture due to Multi-core Architectures resulting ease synchronization with enhanced speed and reliability. Again architectural verification are challenging for these protocols for coherency systems. Hence this project work has come out with complete verification environment for such a complex MESI coherency protocol based on model...
This paper presents a distributed architecture for asynchronously implementing a class of nonlinear signal processing systems as web services, which in turn can be used to solve a broad class of optimization problems. As opposed to requiring specialized servers, the presented architecture requires only the use of commodity database backends as a central resource, as might typically be used to serve...
In the recent years, wireless technology has arised as a promising alternative to ethernet technology as a transmission medium for industrial automation system. This paper presents our wireless solution for industrial application, which is based on wireless LAN (WLAN) system. In this paper, our proposed system on chip (SoC) design and FPGA implementation for industrial wireless local area network...
Oblivious RAM (ORAM) is a technique to hide the access pattern of data to untrusted memory along with their contents. Path ORAM is a recent lightweight ORAM protocol, whose derived access pattern involves some redundancy that can be removed without the loss of security. In this paper, we introduce last path caching, which removes the redundancy of Path ORAM with a simpler protocol than an existing...
Shared memory is a critical issue for large distributed systems. Despite several data coherency protocols have been proposed, the selection of the protocol that best suits to the application requirements and system constraints remains a challenge. The development of multi-coherency systems, where different protocols can be deployed during runtime, appears to be an interesting alternative. In order...
In this paper, the objective is to investigate different performance enhancement attributes in multiprocessors architectures. We investigate the problem of cache hit and cache miss by efficient cache partitioning technique. We improved power efficiency by handling cache misses during data transfer from main memory to cache. The focus is on cache utilization techniques, cache partitioning techniques,...
With the development of semiconductor technology and many-core processors, many-core processors has gradually become mainstream and a hot topic in the field of computer science. With the development of network and all kinds of network applications, the number of network data presents explosive growth, how to achieve the rapid processing of network data has been a problem to be solved. Aimed to resolve...
Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing...
On-chip communication architectures play an important role in determining the overall performance of System-on- Chip (SoC) designs. Communication architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing elements has a major impact on the system's overall average...
The research on network security concentrates mainly on securing the communication channels between two endpoints, which is insufficient if the authenticity of one of the endpoints cannot be determined with certainty. Previously presented methods that allow one endpoint, the authentication authority, to authenticate another remote machine. These methods are inadequate for modern machines that have...
The major applications of multiprocessor system-on-a-chip (SoC) comprises of heterogeneous processors on a single chip. In this kind of integration, major problem is the cache coherence problem i.e. Maintenance of data integrity. In this paper, we propose a record based methodology to remove the cache coherence problem in heterogeneous multiprocessor platforms with shared and private memories. As...
Today's network architectures are not able to cope with the Future Internet requirements, as they are too inefficient, power hungry, and ossified on the TCP/IP paradigm. In order to promote a viable evolution towards new protocols and paradigms, modern network routers should become programmable to allow a flexible management of both traffic flows and power states. In this respect, Software Defined...
Matrix multiplication is one of the most important operations in linear algebra, widely used in many fields of science and engineering. Cannon's algorithm is a classical distributed algorithm for matrix multiplication for two-dimensional meshes. Generally, MPI-IO is used for its I/O requirements. However it has been well documented that MPI-IO performs poorly in a Lustre file system environment. As...
The era of multiprocessor system-on-chip (MPSoC) has brought a new challenge for modern electronic systems. Communication between IP cores and other peripheral in the MPSoC environment is becoming critical which will affect the performance. Network-on-Chip (NoC) is a promising solution for MPSoC communication limitation. Several NoC studies have been reported over the years but only a few discussed...
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