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Nowadays, SoC uses Network on Chip (NoC) to connect its increasing number of building blocks. FPGAs, like SoCs, can use NoC to connect its increasing number of tiles, memories, DSP slices and embedded processors. But one drawback of using NoC is that increasing its router ports will affect the area, power and frequency of the system significantly. For FPGAs to benefit from the NoC approach we have...
This paper presents the power consumption analysis of two different routing architectures for mesh based FPGAs. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexers. This paper highlights and experimentally demonstrates the benefit that can be reached by using multiplexers...
In this paper, we consider FPGA architecture optimization to reduce power consumption. We study two FPGA routing architectures. The first architecture uses bidirectional Switch Box (SB) implemented using back-to-back tri-state drivers. The second one uses bidirectional SB implemented using tri-states and multiplexors. Experimentation shows that when we use bidirectional SB based on tri-states and...
Buffer insertion is a very effective technique to reduce propagation delay in deep sub-micron VLSI interconnects. As design dimension shrinks, more buffers are needed to improve timing performance. However, the buffer itself consumes power and it has been shown that power dissipation overhead due to buffer insertions is significantly high. Many methodologies to optimize propagation delay with power...
Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques are explored: (1) 3D floorplanning, (2) metal...
Power becomes an ever-increasing concern due to the growing design complexity and the shrinking process technology. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. Also power due to the routing resources is a dominant in field-programmable gate arrays (FPGAs). In this paper, we introduce a methodology for...
The development of sustainable and durable ultra-low-power SoC calls for flexibility integration in the design flow. Reconfigurable logic circumvents the intrinsic low speed performances of software processing in microcontrollers but FPGA fabrics to be embedded suffer from a high power overhead compared to dedicated ASICs. We show that, by combining a power-oriented implementation using multi-VT,...
Topology has a significant effect on the most important parameters of a network such as latency and power consumption. In this paper, different topologies are studied and their functions in networks are described. Ultimately, some novel topology are introduced and compared with existing ones in regard of factors such as power and delay. Results of comparisons show that proposed topology perform better...
We propose to partition links in a network-on-chip into multiple segments and use spare wires at the level of each segment to address permanent errors due to manufacturing or wear out defects. Because different segments of the spare wires address different errors from different segments, the proposed reconfigurable link structure can tolerate a larger number of errors with a reduced number of spare...
The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology in current System-on-Chips (SoCs) for integrating a large number of processing elements in a single die. It has the advantage of enhanced performance, scalability and modularity, compared with previous bus-based communication architectures. Recently, A new Triplet-based Hierarchical Interconnection Network (THIN) has been...
In this paper, we propose a new scheme for packet-switched bufferless Networks-on-Chip (NoCs). The goal is to reduce the area and power consumption while providing high performance. In the proposed scheme, we develop a new bufferless routing algorithm. Extensive cycle-accurate simulations have been conducted to show that the proposed scheme delivers a superior performance compared to both traditional...
The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications...
In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the...
Many high-radix Network-on-Chip (NOC) topologies have been proposed to improve network performance with an ever-growing number of processing elements (PEs) on a chip. We believe Clos Network-on-Chip (CNOC) is the most promising with its low average hop counts and good load-balancing characteristics. In this paper, we propose (1) a high-radix router architecture with Virtual Output Queue (VOQ) buffer...
Routing switches are one of key challenges in FPGA Design field. There are several works performed on routing switch design, but the effect of wires in interconnection rarely considered. In this work, switch design methodologies have been investigated. Among these methods, a modified routing switch is proposed which has less delay and power with notice the wires effects.
Recently DPA resistant logic styles are of great concern. As far as we know, each kind of logic style has its own drawbacks. Masking logic styles can easily be attacked by the template attack. For dual-rail logic styles, TDPL can only keep the total power consumption of the whole cycle constant; as for WDDL, it becomes more and more difficult to efficiently match the interconnect capacitances of differential...
Rapid advances in VLSI technology have increased the number of transistors that fit on a single chip to about two billion. In such complex designs, a primary design goal is to limit the power consumption of the chip. Power consumption depends on capacitance, which depends on the length of wires on the chip and the number of vias which connect wires on different layers of the chip. We use ant colony...
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
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