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In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard...
FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. Considering these exclusive properties of FinFETs, the sources of process variations and their effects on FinFET-based...
Highly scaled FinFET SRAM cells, of area down to 0.128 m2, were fabricated using high-kappa dielectric and a single metal gate to demonstrate cell size scalability and to investigate Vt variability for the 32 nm node and beyond. A single-sided ion implantation (I/I) scheme was proposed to reduce Vt variation of Fin-FETs in a SRAM cell, where resist shadowing is a great issue. In the 0.187 m2 cell,...
This paper proposes new methods for SRAM cell design in FinFET technology. One of the most important features of FinFET is that the independent front and back gates can be biased differently to control the current and the device threshold voltage. By controlling the back gate voltage of a FinFET, a SRAM cell can be designed for low power consumption. This paper proposes a new 8T (8 transistors) SRAM...
In this paper, we propose low power and robust 6T SRAM cells. The cells are based on the Vt-control of the cross-coupled inverters of the SRAM cell to reduce leakage power when SRAM is in the idle mode. Using the Vt-control method along with the built-in feedback leads to increasing the SNM. In comparison to a previous work, our schemes have a higher static noise margin (SNM) and lower standby power...
As CMOS technology is dramatically scaled down in recent years, the operation of SRAM becomes one of critical issues for further scaling. In this paper, we have focused on both FD SGSOI and DG (FinFET) devices because of the scaling capabilities, and we have simulated SRAM SNM with discrete dopant fluctuations in the channel regions by 3D simulation. As for SNM, FinFET is a promising candidate up...
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