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Concurrent communication architectures are essential in order to meet ever increasing demand for higher performance of modern-day System-on-Chip (SoC) applications. The behavior of such communication architectures is usually complex and difficult to model. This paper presents a formal modeling approach based on Stochastic Automata Network (SAN) for efficient performance evaluation of concurrent communication...
The progress of manufacturing technology makes the integration of many cores on a single silica substrate possible, which is called chip multiprocessor (CMP). But how to design the fabric on chip is still in discussion. Based on the advantages of scalability, network on chip (NoC) is a promising solution to solve the on-chip interconnection problem. However, it is still a challenge when communications...
Polymorphic processing has the goal of producing a processor combining the advantages of general purpose processing with the significant gains achievable by custom application specific computing. To achieve these ends a novel polymorphic processor architecture is presented. Incorporating networking on a chip (NoC) techniques into the datapath design has the potential to provide noticeable advantages...
This paper presents a reconfigurable Photonic Network on Chip architecture and evaluates its ultra-low latency potential. The latency performance simulation shows a 50% decrease compared to static photonic network on chip.
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissipation. Fortunately, promising gains can be realized via integration of radio frequency interconnect (RF-I) through on-chip transmission lines with traditional interconnects implemented with RC wires. While prior work has...
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