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The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations...
In this paper we make a case for the use of NoC paradigm to develop future FPGAs in which large computational blocks (cores) are connected to each other through a packet switched communication network. We propose a methodology to develop efficient and deadlock free routing algorithms for such NoC platforms which can be specialized for an application or a set of concurrent applications. Application...
A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto...
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