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The 2D mesh network on chip (NOC) is a popular NOC topology because of network scalability and the use of a simple routing algorithm. However, the long distance traffic may suffer from high transmission latency. In this paper, we propose an improved design called the star-type architecture in which the long distance traffic is allowed to traverse an additional second-level mesh. Simulation results...
Although adaptive routing algorithms promise higher communication performance, as compared to deterministic routing algorithms, they suffer from the out-of-order packet delivery problem. In the context of Network on Chip, the area and computational overhead of ordering packets at the destination is high and may reverse any gain achieved through the use of adaptivity of the routing algorithm. In this...
This paper presents a new topology for network-on-chip (NoC) called “Sorena”. The proposed topology is made by merging of 4-node basic models and then connecting edge nodes. Using a change in coordinate system of nodes, a simple, fast and deadlock-free routing algorithm has been suggested. Compared to 2D Mesh which is the most common topology in on chip networks with its high expandability and simple...
Chip multiprocessors (CMPs) have become the primary approach to build high-performance microprocessors. Such systems require fast and efficient communication that can only be realized using network on chip (NoC), particularly for large systems. Allocation and management of on-chip processors are also important factors to achieve high efficiency. Designing processor allocator, job scheduler and NoC...
Topology selection is an important issue for the design of network on chip systems. At present, typical application-specific NoC systems often integrate a number of heterogeneous components which have varied functions, sizes and communication requirements. Instead of regular topology networks which are not suitable for this sort of NoC systems, irregular mesh network is proposed and applied in NoC...
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