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The turn-on behavior of high-voltage-tolerant nLDMOS SCRs is investigated during CDM ESD events. An early failure occurs because of gate-oxide damage. A device optimization is proposed, which improves the CDM ESD robustness up to 2.7x, unchanging the HBM ESD robustness.
A novel and robust transient-assisted high voltage SOI (Silicon On Insulator) IGBT (Insulated Gate Bipolar Transistor) with a parasitic capacitance for Power-Rail ESD clamp circuit in power integrated circuits is proposed in this work. Without using any other external trigger circuits, the triggering voltage of the improved device reduces by 13% in comparison with the conventional device structure...
This is the first published study of the reliability of thyristor-based high-speed memories. The T-RAM (thyristor-based random access memory) was characterized using test structures and multi-megabit product die fabricated in a 130 nm SOI logic technology. The reliability lifetime of a nominal bit was investigated by subjecting TCCT devices (thin capacitively coupled thyristor) to a DC current stress...
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