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Sub-threshold circuit is a promising circuit design style for IoT application, but the timing closure, especially hold timing fixing is a big challenge for designers. This paper proposes a mathematical method to estimate the number of insertion inverters/buffers for hold timing fixing in each short path. Firstly, the distribution of path delay is rigorously proved to be lognormal distribution in the...
Previous work has demonstrated the feasibility of transistor-level symbolic timing simulation, using MTBDDs to share computations across input combinations with similar behaviors. This paper introduces an alternative approach using cached Partial Circuit States paired with simple BDD guards. The proposed approach improves efficiency by decoupling the numerical and Boolean computations required for...
In this paper we review the prior art and recent advances in the area of standard cell modeling for delay and noise analyses, suggest a taxonomy of different cell models, and discuss their strengths and weaknesses. We also discuss challenges in cell modeling for delay and noise analyses arising in new submicron process nodes.
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