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This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
A Hardware Test-Bed (HTB) is developed to serve as a platform for power grid emulation. For maximum flexibility, power converters, which can accommodate various control algorithms and behave distinctively based on the applied model and control, is adopted. With the developed emulators, such as generator, load, wind turbine, and PV emulators, diverse research and experiments can be performed by using...
In this paper, we present an approach to testing of models and generated code as well as of target interpreters that relies on the use of modeling tools and model transformation languages. When compared to the existing Model Driven Development (MDD) approaches and tools supporting Domain Specific Modeling (DSM), contributions of our research include: (i) introduction of action reports, which allow...
For a time invariant system with finite possible events, the possible scenarios are defined by the relative delays between the events. For testing the system, all the nonredundant scenarios need to be generated and utilized. A simple random number generator is inefficient and generates redundant scenarios. In this work, we derive the non-redundant set of scenarios and then propose a method for generating...
An alternative to real-time simulation for hardware-in-the-loop testing is proposed. This involves system simulation, not necessarily done in real time, and real-time playback of the simulated output to the controller under test. The time-stamped controller output is stored and subsequently fed as an input to the simulation. This whole process is done iteratively as in the Waveform Relaxation method,...
An increasing number of Electronic Control Units in passenger cars and high communication traffic have led the car manufacturers to splitting a single CAN network into several dedicated sub-networks running concurrently. Test and evaluation tools for CAN based networks are available for years, but they are mostly focused on test scenarios with up to two CAN networks, often based on the standard CAN...
Modern mixed-signal/RF circuits with digital calibration capabilities could achieve significant performance improvements once the calibration process is completed; however, the calibration time is often very long - in the order of hundreds of milliseconds or even seconds. As testing such devices would require completion of calibration first, lengthy calibration time would result in unacceptably long...
There is a strong demand for both calibrating and testing the ADC performance before and after packaging for mixed-signal SoCs and SiPs. In this paper, we propose a built-in self-calibration scheme that offers digitally-controlled calibration of a pipelined ADC without using external stimulus. We further propose a self-testing strategy that uses the effective number of bits (ENOB) derived directly...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
According to the specified standard of airborne Photogrammetry, digital airborne cameras must have higher performance than ordinary civil cameras, which must shoot with shorter time interval and will generate huge data stream. In this paper, a digital airborne camera is designed and implemented in a single FPGA chip as a SOPC approach. The functions of image acquisition, storage and display are implemented...
Task trees are common notations used to describe the interaction between a user and an interactive application. Thus, they contain valuable information about the expected user behaviour. In this paper, we present a method for automatically generating test data from a task tree. The task tree is extended to support operational profile specification. The user behaviour is automatically extracted as...
The goal of this paper is to provide a basic overview of efficient and powerful approach to testbench construction using an abstract object-oriented framework. Basic testbench environment is reviewed; several corner cases are demonstrated, like synchronization of several transactors working in parallel under SystemVerilog simulation toolsuite.
Testing distributed arrangements of protective devices often requires distributed test equipment for comprehensive assessment. The test units need to be synchronized in order to provide properly interpretable signals to the devices under test. While there are diverse ways to achieve this goal, one efficient way is to make use of IRIG-B signals that are available on site, e.g. for time logging purposes...
MPSS simulates the behavior of a high traffic transaction processing system. An effective use of MPSS is the analysis of the impact of exclusive control of system resources over multiple processes. MPSS consists of a control process and multiple application processes. The control process is designed to simulate a transaction processing monitor. It initiates and oversees multiple application processes...
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