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This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband (IR-UWB) receiver with the sampling rate of 2.112 GS/s. The ADC's specifications are optimized at the system level. Two parallel channels help to achieve high conversion speed and low power consumption. To tackle the problem of clock mismatch between the channels,...
Successive-approximation analog-to-digital converters (SA-ADCs) have recently been widely used for moderate-speed moderate-resolution applications where power consumption is of major concern. In this paper, several techniques are proposed to further reduce the power consumption of an SA-ADC. These solutions include a splitsegmented architecture for the capacitor-based digital-to-analog converter (DAC),...
In this paper, a low power and variable resolution (adaptive) flash ADC is proposed. The ADC enables exponential power reduction while the reduction in resolution is linear. In the proposed design, unused parallel voltage comparators are switched to standby mode leading to consumption of only the leakage power. The ADC, capable of operating at 4-bit, 5-bit, and 6-bit precision, dissipates 6 mW at...
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