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Rather than continue the expensive and time-consuming quest for transistor replacement, the authors argue that 3D chips coupled with new computer architectures can keep Moore’s law on its traditional scaling path.
In this work the authors proposed a multiplier circuit which is one of the important hardware block in most of the digital and high performance systems such as ALU in the microprocessors and controllers. Multiplication is one of the most time consuming operation as a number of bit increase multiplication become cumbersome in the processors. The multiplier architecture proposed in this paper is based...
Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable Architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable...
This paper describes a high assurance architecture for smart metering. Hacking the smart metering infrastructure can have an enormous physical impact, therefore, it is essential that the components in this architecture are proven to be secure. In order for components to be verifiable, however, they need to be sufficiently simple. In this paper, we map the functionalities and different software modules...
The series-stacked architecture provides a method to increase power delivery efficiency to multiple processors. With a series-stack, Differential Power Processing (DPP) is needed to ensure that processor voltages remain within design limits as the individual loads vary. This work demonstrates a switched-capacitor (SC) converter to balance a stack of four ARM® Cortex-A8 based embedded computers. We...
A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, micro processors and digital signal processors etc. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area consuming. The Carry Select Adder (CSLA)...
The Deeply Depleted Channel (DDC) transistor architecture offers 2 to 3 times improvement in body coefficient and 60 percent improvement in local mismatch in 55-nm technology, extending design techniques such as body biasing with voltage scaling to more recent technology nodes. This article presents a body bias architecture for adaptive correction of manufacturing variation, with less than 0.5 percent...
In this paper, we study how to reduce the cache leakage energy efficiently in a hybrid SPM (Scratch-Pad Memory) and cache architecture. Since SPM can reduce the access frequency to the cache, we find it is possible to place the cache lines of the hybrid SPM-cache into the low power mode more aggressively than traditional leakage management for regular caches, which can reduce more leakage energy without...
Merits of Three-Dimensional (3D) integration offer a technology that meet the requirements of the current trend in many-core processors. However, cost is always the dominant factor of adoption of a new technology. After introduction of a fabrication cost model, 2D, homogeneous 3D and heterogeneous 3D architectures are implemented in eight designs. The fabrication costs of these designs are evaluated...
Exploiting computational precision can improve performance significantly without losing accuracy in many applications. To enable this, we propose an innovative arithmetic logic unit (ALU) architecture that supports true dynamic precision operations on the fly. The proposed architecture targets both fixed-point and floating-point ALUs, but in this paper we focus mainly on the precision-controlling...
Although the state-of-the-art multi-core/many-core processors with SIMD extension are getting powerful enough for full software implementation of highly data-parallel application, highly sequential application still requires dedicated hardware for accelerating its performance because it lacks data-parallelism. In this paper, we propose a novel programmable hardware called FlexGrip™, which aims at...
The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations...
While NoCs are efficient in delivering high throughput point-to-point traffic, their multi-hop operation is too slow for latency sensitive signals. In addition, NoCS are inefficient for multicast operations. Consequently, although NoCs outperform busses in terms of scalability, they may not facilitate all the needs of future SoCs. In this paper, the benefit of adding a global, low latency, low power...
Recent advances in all-optical processing is reviewed. New architectures relying on multicast parametric synchronous sampling have the potential to redefine channel multiplexing and demultiplexing that can be scaled beyond Terabit rate. Besides their role in ultrafast channel manipulation, all-optical processors were recently used in wavelength-transparent penalty reversal, opening a new path towards...
This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can...
Power consumption is a critical design issue in embedded processors. One common component in the processor is the register file (RF). RF takes a large portion of processor area and consumes a significant amount of power. This paper proposes a customization approach at the hardware description modeling level to reduce the register file power consumption. The customization does not alter the RF interface...
Network processing devices in future, high-speed network nodes have to be capable of processing several hundred million packets per second. Additionally, they have to be easily adaptable to new processing tasks due to the introduction of new services or protocols. Field programmable gate arrays (FPGAs) and network processors are suitable devices fulfilling these requirements: The former offer configurability...
QR decomposition (QRD) is an essential signal processing task for many MIMO signal detection schemes. However, decomposition of complex MIMO channel matrices with large dimensions leads to high computational complexity, and hence results in either large core area or low throughput. Moreover, for mobile communication applications that involve fast-varying channels, it is required to perform QR decomposition...
Over the past decade, the amount of processing utilized in spacecraft has increased. From below 1 MIP in the 1980s to single digit MIPS in the early 1990s to 10s of MIPS by the end of the twentieth century to hundreds of MIPS today, the amount of processing is in an upward trend paralleling though lagging the commercial and military embedded processing markets. This has allowed processing to move...
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