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It is notoriously hard to verify and debug the final, board-level implementation of FPGA designs. The task involves manual intervention and creativity, unpredictable time costs, and it is further complicated by side-effects of the monitoring circuits inserted into the Design Under Test (DUT). In this paper, we introduce gNOSIS, an automated tool for board-level debugging and verification of FPGA designs...
Developing concurrent programs is intrinsically difficult. They are subject to programming errors that are not present in traditional sequential programs. Our current work is to design and implement a hybrid approach that integrates static and dynamic analyses to check concurrency-related programming errors more accurately and efficiently. The experiments show that the hybrid approach is able to detect...
The Prism model checker facilitates the formal modelling and analysis of systems that exhibit random or probabilistic behaviour. Prism lacks the provision of methods for specification debugging. To help alleviate this problem, we present a tool Prism2Promela for translating Prism into Promela. Once in this form, the SPIN model checker can be used to identify errors in the Promela specification, which...
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