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The proposed multiplier pertaining to concepts of Vedic Mathematics was designed to reduce propagation delay, design complexity as well as to optimize power consumption in comparison to conventional multipliers. A multiplier is a key element in DSP systems, serving as a building block of most computational digital systems, therefore, speed and power consumption are two important parameters of design...
Using fixed-point arithmetic rather than floating-point for data processing can significantly reduce the cost and power consumption of embedded systems. Unfortunately, this also shifts the burden of managing the data representation from run time to compile time, and in many cases the task of compile-time optimization must be done manually. A number of attempts have been made to formalize this process,...
This study presents a high-performance position controller for permanent magnet linear synchronous motor (PMLSM) drives based on FPGA (field programmable gate array) technology. Firstly, a mathematic modeled for PMLSM drive is defined. Secondly, to increase the performance of the PMLSM drive system, an AFC (adaptive fuzzy controller) constructed by a fuzzy basis function and a parameter adjustable...
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