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The security of cryptocircuits is today threatened not only by attacks on algorithms but also, and above all, by attacks on the circuit implementations themselves. These are known as side channel attacks. One variety is the Active Fault Analysis attack, that can make a circuit vulnerable by changing its behavior in a certain way. This article presents an experimental fault insertion attack on an FPGA...
The design and implementation of a frequency meter that operates in real-time is presented. It has been implemented in a low cost FPGA device, concretely, in a SPARTAN-3AN700. The measuring device is configurable in resolution time and in maximum measurable period. The main characteristics of the frequency meter are a minimum resolution time of 2.60 ns and a minimum measurable period of four times...
Modern processor architectures sacrifice timing predictability to improve average performance. Branch prediction, out-of-order execution, and multi-level cache hierarchies complicate accurate execution time estimates. The timing demands of Cyber Physical Systems (CPS) have led some to propose new processor architectures, including Precision Timed (PRET) processors, which simplify analysis of execution...
FPGAs have been mainly used for designing of synchronous controllers. However, it is difficult to design asynchronous controllers on them because the circuit may suffer from hazard problems. This paper presents a method that implements a class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. Asynchronous controllers specification used in heterogeneous (synchronous...
This paper presents a processor for timing signal generation, developed to provide the capability to generate the real-time control signal outputs through software programming. Using the proposed processor, we also developed a low cost and flexible timing signal generator for driving PDP system. The proposed timing signal generator adopts efficient architecture to control the PDP operations, implemented...
OFDM Wireless systems are currently in the focus of research and development. High hardware cost of such systems is an initiative to redesign the critical functional blocks in order to satisfy timing and power constrains as well as to minimize overall circuit complexity and cost. One such critical functional block is the CoOrdinate Rotation DIgital Computer (CORDIC) that can be used in various applications...
This paper proposes a novel preamble structure and a timing synchronization method for OFDM systems. The preamble structure has both properties of delayed and symmetric correlations which can afford accurate time and frequency synchronization simultaneously. A new timing metric is also proposed according to the preamble structure, which is the production of the modulus of delayed and symmetric correlation...
In this paper, we present an efficient HW/SW codesign architecture for H.263 video coder and its FPGA implementation. Each module of the coder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portion include the discrete cosine transform (DCT) and inverse DCT (IDCT). Remaining parts were realized in software...
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