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Initially, FGMOS gate stack is examined for satisfactory memory behaviour. Later, we present a simple analytical model for the low frequency capacitance of a quantum dot based flash memory gate stack. The model makes use of simple parallel combination of capacitances offered by differentiating regions formed in the gate stack of a flash memory. The model describes overall capacitance where dimensions,...
Cell-to-cell interference in charge trap based TANOS (Tantalum-Alumina-Nitride-Oxide-Silicon) NAND flash memory was investigated. Bit-line (B/L) interference is larger than word-line (W/L) one, which means that the channel coupling by adjacent program string to inhibit string gives larger effect than capacitive coupling to adjacent nitride storage nodes along the string. By separating the total Vth...
Abstract-We propose a cell structure with monocrystalline floating gate and 6 nm to 8 nm of thermally grown SiO2 interpoly dielectric (IPD) for <20 nm NAND Flash arrays. This thin IPD avoids the bitline pitch scaling barrier caused by the ONO thickness limitation. Simulations show that, down to the 12 nm node, such cells can be programmed without excessive IPD leakage. The combination of modeling...
In this paper, we propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the sidewall control pillar (SCP). This novel cell consists of cylindrical FG and SCP with a line type control gate (CG) structure. For simplifying the process flow, we propose to fabricate the cylindrical SCP structure by using the self-aligned process with the deposition of...
The scaling of floating gate cell has been the key driving force in NAND flash market growth over the past two decades. However, the scaling of conventional floating gate technology below 20nm is looking to be very difficult due to some physical and electrical issues. Critical issues of scaling in NAND flash memory technology below 20nm are reviewed. The possible solutions for overcoming scaling challenges...
We developed the new control gate (CG) material and structure in order to overcome scaling limitation beyond 20nm NAND flash cell. New CG material can achieve excellent gap-fill without void and improvement of the Gate CD Gap (GCG). And also, by using new CG material, CG depletion between floating gate (FG) can be improved. As a result, gate coupling ratio, bit-line (BL) interference and tail-cell...
We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work...
Nanoscale charge trap flash (CTF) memory devices with a metal spacer layer were designed to decrease the interference effect and to increase the fringing field effect and the coupling ratio. The optimum metal spacer depth of the memory devices was determined to enhance the device performance of the memory devices. The drain current and the threshold voltage shifts of the CTF memory devices were increased...
We propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the Separated - Sidewall Control Gate (S-SCG). This novel cell consists of one cylindrical FG with a line type control gate (CG) and S-SCG structure. For simplifying the process flow, we realized the common S-SCG lines by using the pre-stacked poly silicon layer, through which variable medium...
We intensively investigated the interference effect by direct or indirect coupling path with neighboring cells of the 3-Dimensional (3-D) vertical Floating Gate (FG) type NAND cell arrays. Above all, we proposed the optimum 3-D vertical FG type NAND cell array structure to fully suppress the interference effects.
As the NAND flash memory market grows rapidly due to various applications, such as USB devices, MP3 players, SSDs, cellular phones, and cameras, there is a requirement for high-density and low-cost devices. Two different approaches to meet these requirements are increasing data per cell and area scaling. 3b/cell or 4b/cell NAND flash memories were introduced as an effective way to lower cost. However,...
A highly reliable 26nm 64GB MLC E2NAND (E2: Embedded-ECC & Enhanced-efficiency) flash memory has been successfully developed. To overcome scaling challenges, novel integration and operation technologies, such as 2-dummy word-line (WL) scheme, depletion suppressing process, hydrogen reducing process and Virtual Negative Read (VNR) scheme are introduced. And also, Memory Signal Processing (MSP)...
The NAND flash market is continuously growing by the successive introduction of innovative devices and applications. To meet the market trend, 3-dimenstional (3D) non-volatile memories (NVMs) are expected to replace the planar one, especially for 10 nm-nodes and beyond. Therefore, the fundamentals and current status of the 3D NAND flash memory are reviewed and future directions are discussed.
We propose the novel 3-dimensional (3-D) vertical floating gate (FG) NAND flash memory cell arrays with novel electrical source/drain (S/D) technique using Extended Sidewall Control Gate (ESCG). Cylindrical FG structure cell is implemented to overcome the reliability issues of the charge trap cell such as SONOS and TANOS cell. We also propose the novel electrical S/D layer using the ESCG structure...
Self-aligned shallow trench isolation recess effect on 42 nm node NAND flash to achieve high performance and good reliability has been studied and demonstrated. As cell STI recess is increased by 23 nm, 29% narrower cell Vth distribution width and 54% less cell Vth shift after 125°C, 2 hours can be obtained. Furthermore, the endurance window is obviously improved ~0.5V as the distance of the active...
Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and...
In this work, we have successfully demonstrated SONOS memories with embedded Si-NCs in silicon nitride by in-situ deposition method. The self-assembly silicon nanocrystals were in-situ deposited within the Si3N4 storage layer by dissociation of dichlorosilane (SiH2Cl2) gas to a high density of 9 times 1011 cm-2. This new structure exhibits larger memory windows for up to 6 V, better program/erase...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
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