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With development of semiconductor fabrication technology, channel length of CMOS device and device pitch scale down accompanied by more severe process variation and signal coupling effect. In this paper, we focus on the decouple latch type voltage sense amplifier which is widely used in SRAM product. Two main signal coupling effects are introduced and analyzed, and improved design is suggested
The traditional static fault tree cannot capture the dynamic behavior of system fault mechanisms, so the dynamic fault tree has become one research hot spot now. Many scholars focus on the research of using the dynamic fault tree model and analyze for dynamic behavior of system fault mechanisms. However, in their studies they generally separate the software and hardware and analyze independently....
There are lots of studies regarding methods of coding the information sent via a parallel data bus from inside a chip. As a result of shrinking the gadgets, the traces from an off-chip bus are getting closer, and the coupling capacitance is increasing. The traces from an off-chip bus are much longer than the ones from an on-chip bus, so a new study is necessary to analyze how crosstalk affects off-chip...
In this work, the interface coupling in short-channel Multiple-gate MOSFETs (MuGFETs) structures is modelled. Based on the solution of the 3D Laplace's equation, the short-channel subthreshold characteristics (Subthreshold current, Subthreshold Slope, Roll-off and DIBL) are calculated and compared to experimental data with an excellent agreement, and without the need of any fitting parameters. The...
In this paper, we report the impact of the parasitic capacitances in the modeling and analysis of advanced floating gate (FG) non-volatile memory (NVM) devices, especially on the coupling ratio. Due to the poor accuracy of the existing capacitance model when compared to practice, an approach to include the parasitic capacitances has been established. Measurement results from two transistor (2T) Fowler-Nordheim...
Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk is one of the major causes for such kind of failures. Typically, crosstalk faults result from switching of neighboring lines that are capacitively coupled. As we move deep into nanometer regime, transistor gate leakage introduces considerable...
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Channel mismatch, including amplitude and phase mismatch, has severely affected the performance of space-time adaptive processing (STAP). In order to ascertain the specification of the effects on STAP, theory analysis of relation between clutter covariance matrix (CCM) with and without channel mismatch is done based on the model provided by literature, and the effect to signal is also analyzed. In...
Modern business process modeling languages such as BPMN or EPC provide users with more constructs to represent real world situations than their predecessors such as IDEF or Petri Nets. But this apparent increase in expressiveness is accompanied by an increase in language complexity. In practice many organizations choose to only use a subset of the available modeling constructs. Using a well established...
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