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This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS...
A 1.8V 12bit 100MS/s pipelined ADC in 0.18um CMOS process is presented. The first stage adopts 3.5-bit structure to relax the capacitor matching requirements. Bootstrapped switch and scaling down technique are used to improve the ADC's linearity and save power dissipation respectively. With a 2.4 MHz input signal, the ADC achieves 68.9dB SFDR and 9.3 ENOB at 101MS/s. The power consumption is 180mW...
A new high-voltage bootstrapped sampling switch with input signal range exceeding 11 times its supply voltage is presented. Proposed switch occupies a silicon area of 250 mum by 160 mum in 0.35 mum twin-well CMOS process with drain extended NMOS (DNMOS) capability. The switch safe input signal range is restricted only by the DNMOS drain terminal breakdown voltage, i.e. 50 V . Implemented switch can...
This paper reports a highly linear RF sampler with wide operating frequency range and power supply range. A clock bootstrapping circuit is proposed to decrease both the on-resistance and off-leakage of advanced MOSFETs while considering the device reliability. The proposed RF sampler circuit has been implemented in 90 nm CMOS process, and excellent IIP3 has been obtained at wide frequency range up...
A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough...
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