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The scaling of CMOS technologies towards nano-scale size nodes brings up critical design challenges such as parameter variability mitigation and device aging control along the chip lifetime. The combination of these phenomena leads to a time-dependent variability of the electrical properties of the device, which can significantly impact the performance, yield and reliability of the circuits and systems...
As process technology scales down, circuit delay variations become more and more serious due to manufacturing and environmental variations. The delay variations are hardly predictable and thus require additional design margin and impede the chance to reduce area and power consumption of a chip. One way to alleviate the problem is to measure the circuit delay at run-time and control the supply voltage...
In-situ DC measurements of individual transistors in a differential pair of an analog amplifier derive threshold voltage, Vth, of 1.0-V transistors in a 90-nm CMOS technology. On-chip continuous time waveform monitoring is used to evaluate AC response of the same amplifier. The distribution of AC gain versus Vth of transistors within amplifiers is captured. The degradation of common-mode rejection...
This paper reviews recent experimental confirmations that the intrinsic radiation robustness of commercial CMOS technologies naturally improves with the down-scaling. When additionally using innovative design techniques, it becomes now possible to assure that performance and radiation-hardness are both met. An illustration is given with an original nano-power and radiation-hardened 8 Mb SRAM designed...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
Minimizing the area of a circuit is an important problem in the domain of Very Large Scale Integration. We use a theoretical VLSI model to reduce this problem to one of laying out a graph, where the transistors and wires of the circuit are identified with the vertices and edges of the graph. We give an algorithm that produces VLSI layouts for classes of graphs that have good separator theorems. We...
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