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Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different core, reducing the execution time and potentially its worst-case execution time (WCET). Unfortunately, inter-thread interferences generated by simultaneous accesses to shared resources...
As the increasing in chip density, on-chip communication will be a key factor in determining the performance and power consumption of the multi-core processor. Some typical communication mechanisms of the multi-core processor at present are introduced in detail in this paper, such as cache-shared bus structure, shared-bus structure and NoC-based structure, and there advantages, disadvantages and ranges...
In the era of multi-core processors, the challenge of designing a high efficient memory system is more severe than before. This paper focuses on the memory hierarchy design and implementation on a multiprocessor system. With the distributed shared memory (DSM) model, some techniques have been presented to improve the performance of traditional memory hierarchy and simplify the complexity of cache...
In a multicore processor, different cores typically share the last level cache, and threads running on different cores may interfere with each other in accessing the shared cache. Therefore, multicore WCET (worst case execution time) analyzer must be able to safely and accurately estimate the worst case interthread cache interferences, which is not supported by current WCET analysis techniques that...
Load balancing is an important problem for parallel applications. Recently, many super computers are built on multi-core processors which are usually sharing the last level cache. On one hand different accesses from different cores conflict each other, on the other hand different cores have different work loads resulting in load unbalancing. In this paper, we present a novel technique for balancing...
The best interface between CPUs and reconfigurable hardware in heterogeneous systems remains an open question. The trend in multi-core processors is to communicate through a shared memory hierarchy; but cache organizations that work best for general-purpose multi-core systems may not be best for heterogeneous systems. In this paper we explore a variety of cache topologies for connecting a CPU with...
Multi-core processor is widely used on the server and desktop computer nowadays. This paper describes the structure of a cache crossbar which used in the multi-core processor SPARC T2. The cores can use the cache crossbar to exchange the data in the L2 cache banks. The multi cores can communicate among each other core by sharing the data in the L2 cache banks. And with the analysis of the CCX, this...
Simultaneous multithreading (SMT) is becoming one of the major trends in the design of future generations of microarchitectures. Its key strength comes from its ability to exploit both thread-level and instruction-level parallelism; it uses hardware resources efficiently. Nevertheless, SMT has its limitations: contention between threads may cause conflicts; lack of scalability, additional pipeline...
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