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The performance analysis and comparison of 2×4 network on chip (NoC) topology are mainly presented in this paper. Firstly, three common 2×4 topologies, 2D Mesh topology, 2D Torus topology and hierarchical Mesh topology are designed. Secondly, the performances of three topologies are analyzed and compared in detail by using NoC performance evaluation standard. Finally, the occupying resources of three...
Design and Implementation of network on chip interconnection architecture for eight compute-intensive processors are mainly presented in this paper. Firstly, through analysis and comparison of three common NoC topologies, 2×4 2D Turos is chosen as the final topology, and the single routing node architecture is designed, including packet format, routing and arbitration. Secondly, routing nodes coding,...
As the increasing in chip density, on-chip communication will be a key factor in determining the performance and power consumption of the multi-core processor. Some typical communication mechanisms of the multi-core processor at present are introduced in detail in this paper, such as cache-shared bus structure, shared-bus structure and NoC-based structure, and there advantages, disadvantages and ranges...
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