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Cu/low-k interconnects have been used in LSI fabrication. However, several difficult challenges need to be overcome for 22-nm node devices and beyond. These challenges include an increase in resistivity, degradation of the electromigration reliability, and the low mechanical strength of low-k dielectrics. To overcome these problems, it is essential to not only improve Cu/low-k fabrication processes...
The on-chip interconnect bottleneck with conventional Cu/low-k and delay optimized repeater scheme presents a compelling reason to explore novel interconnect circuit architectures. The capacitively driven low-swing interconnect (CDLSI) has the potential to affect a significant energy saving and latency reduction. The purpose of this work is two fold: Firstly, to develop an accurate analytical, optimized...
The on-chip global interconnect with conventional Cu/low-k and delay-optimized repeater scheme faces great challenges in the nanometer regime owing to its severe performance degradation. This paper describes the analytical models and performance comparisons of novel interconnect technologies and circuit architectures to cope with the interconnect performance bottlenecks. Carbon nanotubes (CNTs) and...
The scaling of the integrated circuits foreseen by the technology roadmap imposes tight requirements to the interconnects, in terms of latency, energy density and bandwidth. Innovative solutions are proposed to replace the traditional copper technology at nanometric scale. In this paper we investigate the behavior of some of these innovative interconnects, namely carbon nanotube interconnects, arrays...
Glass is a potential substrate material for the manufacture of substrates for high density electrical and optical interconnect. However, in order to realize such substrates, metallization is required to form conductive tracks and pads. In this work, electroless copper was used due to its relatively low cost, fast speed and potential for high volume production. Silanisation of the glass surfaces with...
Several technological and architectural solutions have been proposed to solve the "interconnect performance bottleneck", such as the use of on-chip transmission lines, carbon-nanotube (CNT) interconnects, wafer-level package (WLP) interconnects, 3D interconnects, RF and microwave interconnects and optical interconnects. It is essential to accurately estimate the interconnect performance...
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