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Using independent voltage (and frequency) domains for cores and caches allows us to achieve high energy efficiency since it enables operating the cores and caches at their own optimal voltages. However, it incurs a clock synchronization problem between the core and cache voltage domains. One of the conventional solutions is to add asynchronous FIFOs on the domain crossing boundary, but it degrades...
This paper describes the architecture and design of high-speed clock recovery circuit for burst-mode applications. Since the proposed circuit is non-PLL-type and designed in fully digital style, it can provide faster acquisition time, better scalability and portability compared to PLL-type or analog style clock recovery circuits. The proposed circuit recovers output clock for every transition of input...
Clock skew optimization continues to be an important concern in circuit designs. To overcome the influence caused by PVT variations, the automatic skew synchronization scheme can dynamically adjust and reduce the clock skew after a chip is manufactured. There are two key components in the skew synchronization scheme: Adjustable Delay Buffer (ADB) and Phase Detector (PD). Most previous researchers...
High speed serial interfaces represent the new trend for device-to-device communication. These systems require clock recovery modules to avoid clock forwarding. In this paper we present a high-speed clock recovery method usable with low-cost FPGAs. Our proposed solution features increased speed and reduced size compared to existing designs. The method allows a maximum throughput of 400 Mbps compared...
This paper deals with the comparison of the analog and digital phase-locked loops that use identical LC VCO. Both circuits were designed and simulated in CMOS AMS 0.35 μm (3.3 V) technology using full-custom technique. The centre frequency of the oscillator is about 1.1 GHz. The analog loop consists of the Gilbert multiplying phase detector and active low-pass filter while digital one is built of...
This paper refers with autosynchronous state machines from basic parameters and timing properties determination to design methodology description. Firstly the timing conditions are determined based on comparison with synchronous state machines timing. Next section describes design methodology. In this section the additional parts like stable state detector and local clock generator are introduced...
This paper describes a clock skew variation compensating technique for maintaining the skew amount between local clock meshes which have relative skew between them due to PVT variations and unbalanced load distribution. A skew detector that senses skew amount between clock meshes and converts it to effective logic values with a digitally controlled delay set which corrects the clock skew of the meshes...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
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