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In this paper, we propose self-contained built-in-self-test/repair (BIST/R) solutions to improve the reliability of the direct face-to-face copper thermo-compression bonding A dual-mode transceiver is presented to operate either as an ohmic mode when the bonding has low resistance or as a capacitive coupling mode when the bonding is faulty showing high resistance.
The FinFET technology is considered as the best candidate to extend the CMOS technology down to 10 nm. In this paper, a three-dimensional (3-D) parasitic extraction flow is proposed for modeling and timing analysis of the FinFET based circuits. The flow fully considers the 3-D geometry of the FinFET and employs accurate field solvers for extracting resistances and capacitances. Thus, it accurately...
The aim of this paper is to predict the performance of local interconnects, manufactured by advanced patterning options as double patterning and EUV lithography. Electrical wire parameters as resistance, capacitance, RC delay and coupling between adjacent wires are extracted by simulation from scaled 2-D interconnect models, calibrated with dimensions and electrical parameters measured on simple test...
Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32 nm and 22 nm process nodes, relative to costlier technology options such as high refractive index materials, extreme ultraviolet (EUV), or e-beam lithography. DPL implements patterns on a single layer using either additional masks (e.g., double exposure or double patterning) or many additional...
Process induced variations in the interconnect capacitance and resistance have resulted in significant uncertainly in the interconnect delay. In this work, we propose a new method to compute the interconnect corner considering coupling-noise due to simultaneous switching of aggressors. In prior approaches, the interconnect corners were computed under the assumption that the aggressor nets are not...
Design guidelines for shielding in the presence of power/ground (P/G) noise are presented in this paper. The effect of noise in the P/G network is analyzed for various line lengths, line widths, and interconnect driver resistances. A 2pi RLC model is used to investigate the effect of both coupling capacitance and mutual inductance on the crosstalk noise. For a range of shield lengths and widths, a...
This paper proposes a new approach to analyze crosstalk of coupled interconnects in the presence of process variations. The suggested method translates correlated process variations into orthogonal random variables by principle component analysis (PCA). combined with polynomial chaos expression (PCE), the technique utilizes Stochastic Collocation Method (SCM) to analyze the system response of coupled...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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