The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Layout pattern classification has been utilized in recent years in integrated circuit design towards various goals such as design space analysis, design rule generation, and systematic yield optimization. There is a need for open source or academic solutions as very limited vendors are available to provide this functionality. Speed and accuracy are key aspects to target in the solutions. Given a circuit...
Throughput is one of the major limitations of E-beam inspection. Compared to broad-band plasma inspection, the throughput may be 1000x less. To address this limitation, E-beam inspection tool manufacturers continue to advance single-column inspection tool technology. In parallel, there are a number of efforts to develop multi-column E-beam inspection tools. Both these paths will take time and require...
As we approach single-digit nodes, traditional design for manufacturability is augmented through several methodologies and design paradigms such as design-technology co-optimization (DTCO), systematic yield limiters optimization (SYLO), and design retargeting. We discuss triple-patterning and spacer-based multiple patterning and their design implications as these technologies will be necessary to...
We introduce the fill optimization problem and benchmarks. We provide two new hotspot definitions, slot line deviation and outliers, both of which pertain to yield. We provide the inputs, expected output, as well as objectives and constraints of the problem.
Increasing delay of interconnects over devices at advanced nodes indicates a need for drastic change for interconnect. Such drastic changes have traditionally been possible through material changes. However, an alternative change in design may be near. In particular, on-chip optical interconnections are on the verge of being introduced to be able to cope with system-scale performance roadmaps. Thereby,...
FinFETs have proven to be the device of choice for the next few technology generations. Consequently, design rules and limitations related to FinFETs need to be carefully understood. We present restricted and gridded design rules related to FinFETs. We also present results which indicate that a complete front-end-of-line (FEOL) and middle-of-line (MOL) of a memory with controllers can be designed...
Modeling layout-dependent interconnect processing steps is useful to predict integrated circuit design behavior. We illustrate key data and steps in developing etch, electrochemical deposition (ECD), and chemical-mechanical polishing (CMP) models in order to predict chip topography. We utilize an interferometer for validation of models for the first time. Such models are useful to select optimal fill...
Graphical processing unit (GPU) computing has been an interesting area of research in the last few years. While initial adapters of the technology have been from image processing domain due to difficulties in programming the GPUs, research on programming languages made it possible for people without the knowledge of low-level programming languages such as OpenGL develop code on GPUs. Two main GPU...
The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results...
Double patterning lithography (DPL) provides an attractive alternative or a supplementary method to enable the 32 nm and 22 nm process nodes, relative to costlier technology options such as high refractive index materials, extreme ultraviolet (EUV), or e-beam lithography. DPL implements patterns on a single layer using either additional masks (e.g., double exposure or double patterning) or many additional...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.