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EM injection recently emerged as an effectivemedium for fault injection. This paper presents an analysisof the IC susceptibility to EM pulses. It highlights that faultsproduced by EM pulse injection are not timing faults butcorrespond to a different model which is presented in thispaper. This model also allows to explain experimental resultsintroduced in former communications.
In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology. Defining low power test methodology is the need of the day. In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST. The implemented core has given Power, Area advantage of 95.44%, 23.95% respectively but with increased Timing...
Modern SRAM-based Field Programmable Gate Arrays (FPGAs) are increasingly employed in safety- and mission-critical applications. However, the aggressive technology scaling is highlighting the increasing sensitivity of such devices to Single Event Upsets (SEUs) caused by external radiation events. Assessing the reliability of FPGA-based systems in the early design stages is of upmost importance, allowing...
In System-On-Chip environment, significant changes in testing methods are to be done for memory arrays. The failures in such memories are expensive due to wastage of large die area. This paper presents a Built-In-Self-Repair Analyzer with optimal repair rate for memory arrays using redundancy. The proposed method requires only a single test even for worst case. The Must-Repair-Analysis (MRA) technique...
Effective testing to ensure the reliability of integrated circuit (IC) is particularly important, especially in military, aerospace, communications, and other felds. A traditional circuit test structure is shown in Figure 1. Test stimuli are applied to the circuit under test (CUT), and test responses are analyzed so as to determine any fault exists. Traditional testing is faced with several serious...
In modern day, embedded memory density and area on-chip is increasing, it is essential to define new test algorithms which fulfill the need of detecting new faults. The existing March algorithms consist of as many as four or seven operations per March element. In this paper we have presented an optimization of architecture which can implement these new March BLC tests having number of operations per...
The SPACES project is a Japanese-French joint research project that aims to establish a new security evaluation methodology for cryptographic devices. We introduce one of the SPACES project outcomes associated with the development of the security evaluation platform for cryptographic devices. The new feature of the proposed system is to include a newly-developed Side-channel Attack Standard Evaluation...
The paper aims at demonstrating experimentally that the tiny Electro Magnetic (EM) coupling between the tip end of a micro-antenna is sufficient to locally and directly inject power into CMOS Integrated Circuits (IC). More precisely, experimental results show that such electrical couplings are sufficient to disturb, with and without removing the IC package, the behavior of 90nm CMOS Ring Oscillators,...
This paper proposes a unified delay test architecture, in which the design resources for on-line delay fault detection can be reused to support off-line delay testing. A stability checker, which has low hardware overhead, is presented to monitor the stability violation from each critical combinational output. A global error generator, which is shared among stability checkers, can produce a global...
A common scenario in industry today is “No Trouble Found” (NTF) due to functional failures. A component on a board fails during board-level functional test, but it passes the Automatic Test Equipment (ATE) test when it is returned to the supplier for warranty replacement or service repair. To find the root cause of NTF, we propose an innovative functional test approach and DFT methods for the detection...
As embedded memory area on-chip is increasing and memory density is growing, problem of faults is growing exponentially. This necessitates defining of novel test algorithms which can detect these new faults. March Tests belong to the newer line of testing algorithms which offer to detect these exponentially escalating faults. Most of these new March algorithms consist of as many as five or six operations...
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions...
In many synchronous digital systems especially those used in mobile applications, the system is exposed to sever shaking that may lead to a failure in the clock generator. In this paper we present an effective method to tolerate the faults on the clock signal that are due to defects in external oscillators. Our technique utilizes no Phase-Lock Loops (PLL), no Delay-Locked Loops (DLL) and no high frequency...
ATPG patterns of a digital sequential circuit contain temporally and spatially ordered bits as well as random (or donpsilat care) bits. We synthesize BIST hardware that mimics these characteristics by controlled mixing of spectral components and noise. A Hadamard digital wave generator circuit produces all required spectral sequences and a weighted pseudorandom bit generator provides random bits....
Fault diagnosis has recently become an important issue in IC production test because of the need to enforce high manufacturing yield. Furthermore, fault diagnosis is a pre-condition for any technology of built-in self repair that may be used in the field of application where long-time dependable systems are necessary. An "embedded" diagnostic self test has to get along with a minimum of...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
Due to their reconfigurability and their high density of resources, SRAM-based FPGAs are more and more used in embedded systems. For some applications (Pay-TV,Banking, Telecommunication ...), a high level of security is needed. FPGAs are intrinsically sensitive to ionizing effects, such as light stimulation, and attackers can try to exploit faults injected in the downloaded configuration. Previous...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
Cryptographic devices are recently implemented with different countermeasures against side channel attacks and fault analysis. Moreover, some usual testing techniques, such as scan chains, are not allowed or restricted for security requirements. In this paper, we analyze the impact that error detecting schemes have on the testability of an implementation of the advanced encryption standard, in particular...
A novel scheme for reducing the test application time in accumulator-based test-pattern generation is presented. The proposed scheme exhibits extremely low demand for hardware. It is based on a decoder whose inputs are driven by a very slow external tester. Experimental results on ISCAS benchmarks substantiate a test-time reduction of 75%-95% when compared to previously published test-set embedding...
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