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This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small...
A ring oscillator physical unclonable function (RO PUF) is an application-constrained hardware security primitive that can be used for authentication and key generation. PUFs depend on variability during the fabrication process to produce random outputs that are nevertheless stable across multiple measurements. Unfortunately, RO PUFs are known to be unstable especially when implemented on an Field...
The main motto of every electronic industry is to achieve low power. An efficient way to achieve this is by adapting different architectural modifications in the design. This paper proposes low power implementation of Logarithmic Number System (LNS) arithmetic unit on a FPGA. Power reduction is achieved by partitioning technique. The influence of partitioned memory on the power dissipated and delay...
Ring Oscillator (RO) Physical Unclonable Function (PUF) is one of the most popular silicon PUFs which exploit manufacturing variations during the chip fabrication process. RO PUF can generate secret bits by comparing the frequency difference between two ROs. However, previous RO PUFs improve flexibility and reliability through adding redundant ROs and thus incur unacceptable hardware overheads. In...
This paper presents an architecture of system Verilog assertions (SVA) synthesis compiler, which translates the un-synthesizable System Verilog assertions, into synthesizable equivalent Verilog modules, in order to convert them to digital hardware circuits, used to watch how the running design performs. The proposed architecture is based on two main rules: "Simple compiler structure" and...
The present title discloses novel concept for high speed computing using essentials of Ancient Indian Vedic Mathematics, modified and implemented using VLSI-FPGA architecture for best performance. The proposed architecture aims to define highly optimized multiplier unit which allows the highly intensive units of Signal Processing, Image Processing, Data Encryption/ Decryption and most other techniques...
A high performance substitution box (S-Box) FPGA implementation using Galois Field GF (28) is presented in this paper. An optimum number of pipeline registers based on Spartan-3E FPGA is addressed in this paper. The design is fully synthesizable using Verilog and can easily be converted to ASIC implementation. As a result, a fast and area efficient implementation of pipelined S-Box was synthesized...
Floating-point arithmetic is ever-present in computer systems. All most all computer languages has supports a floating-point number types. Most of the computer compilers called upon floating-point algorithms from time to time for execution of the floating-point arithmetic operations and every operating system must be react virtually for floating-point exceptions like underflow and overflow. The double-precision...
This paper presents a Single-path Delay Feedback (SDF) architecture for implementing a Fast Fourier Transform (FFT) processor on FPGA for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing. An FPGA resource efficient and shared multiplier technique for parallel processing of two and four data streams is demonstrated and utilized for realization within the presented SDF architecture...
Floating point multiplication is a crucial operation in high power computing applications such as image processing, signal processing etc. And also multiplication is the most time and power consuming operation. This paper proposes an efficient method for IEEE 754 floating point multiplication which gives a better implementation in terms of delay and power. A combination of Karatsuba algorithm and...
Obfuscation is a technique which makes design less intelligible in order to prevent or increase reverse engineering effort. In this paper, a new approach to hardware obfuscation by inserting constant value generators (CVGs) is proposed. A CVG is a circuit that generates the same fixed logic value but will not be minimized by the synthesizer. CVGs can be used to create new logic primitives, embed watermarks...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
We have developed the first FPGA-based digital physical unclonable function (PUF) by leveraging the reconfigurability of an FPGA and introducing a new way of using the standard analog delay PUF. The key observation is that for any analog delay PUF, there is a subset of challenge inputs for which the PUF output is stable regardless of operation and environmental conditions. We use only such stable...
This paper presents a dynamically configurable and area-efficient multi-precision architecture for Floating Point (FP) division. FP division is a core arithmetic in scientific and engineering domain. We propose an architecture for double precision (DP) division which is also capable of processing dual (two-parallel) single precision (SP) computation, named as DPdSP FP divider. The architecture is...
This paper presents a decimal adder which is hardware, speed and power efficient. Conventional BCD addition usually concludes by adding the correction bits to the result, which often proves to consume lot of processing latency, hence instead of adding correction bits appropriate flag bits are generated thus reducing the delay and the hardware encountered decimal correction. Various fast adders like...
Awareness of the available resources in FPGA platform can improve the quality of the hardware design. Decimal array multipliers due to their regular nature and compatibility with the CLB structure of FPGA platform are suitable cases to this aim. In this paper, PPG unit of a decimal multiplier has been realized using two different approaches in order to improve utilization of the FPGA resources.
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