The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The design of a multiscroll chaotic oscillator based on the realization of a sawtooth function by using floating gate MOSFETs (FGMOS), is introduced. Basically, we propose the implementation of a FGMOS inverter to generate the nonlinear functions which are responsible of the equilibrium points of a continuous chaotic dynamical system, allowing the generation of multiple scroll attractors. Spice simulations...
Adiabatic logic saves energy compared to static CMOS by charging the outputs efficiently and by recovering charge from the outputs. For the most promising adiabatic logic families a four phase power-clock is used, that can be generated in an energy efficient manner by using a synchronized 2N2P LC oscillator. Different input patterns to the circuit lead to different capacitive loads seen by the oscillator...
Hybrid CMOS-SET architectures, which combine the merits of CMOS and SET (single-electron tunneling) devices, promise to be a practical implementation for nanometer-scale circuit design. In this work we propose two binary full adders using hybrid CMOS-SET parallel architectures, which take advantage of the Coulomb oscillation with SET devices in order to improve the circuit area, power consumption...
Digital CMOS circuits are praised because of their noise immunity. However, lowering power supply voltages and shrinking device sizes, in combination with the rising electromagnetic pollution, have made this statement no longer true. An accurate behavioral model is presented for the analog simulation of digital logic circuits. The model building is automated and scalable in the sense that it allows...
A novel Schmitt trigger circuit, implemented by a RS trigger and two simple distinct inverters, is proposed. Its trigger levels are determined by two CMOS inverters. Contrasted with traditional six transistors Schmitt trigger, its temperature and supply voltage characteristics have been analyzed. Apply these two triggers into relaxation oscillator and the result shows that the proposed one in this...
In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (VDD) for logic circuits, the dependence of minimum operating voltage (VDDmin) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm CMOS ring oscillators (RO's). The measured average VDDmin of inverter RO's increased...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.