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Adaptive radiotherapy is a technique intended to increase the accuracy of radiotherapy. Currently, it is not clinically feasible due to the time required to process the images of patient anatomy. Hardware acceleration of image processing algorithms may allow them to be carried out in a clinically acceptable timeframe. This paper presents the experiences encountered using high-level synthesis tools...
The Kalman Filter is a robust tool often employed as a plant observer in control systems. However, in the general case the high computational cost, especially for large system models or fast sample rates, makes it an impractical choice for typical low-power microcontrollers. Industry trends towards tighter integration and subsystem consolidation point to the use of powerful high-end SoCs, but this...
Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a concept that...
This paper presents a new hardware coprocessor to accelerate applications developed using the Notification-Oriented Paradigm (NOP). A NOP application presents the advantages of both event-based programming and declarative programming, enabling higher lever software development, improving code reuse, and reducing the number of unnecessary computations. Because a NOP application is composed of a network...
Recent trends toward increased flexibility and configurability in emerging applications present demanding challenges for implementing systems that incorporate such capabilities. The resulting application configuration space is generally much larger than any one hardware implementation can support. We present an overview of a new data-adaptive approach to rapid design and implementation of such highly...
Codes that have large/irregular-stride (L/I) memory access patterns often perform poorly on mainstream clusters because of the general purpose processor (GPP) memory hierarchy. In the event of erratic access of data, the cache suffers misses and causes inadequate performance of the kernel. High performance heterogeneous computers (HPHCs) are parallel computing clusters that contain multiple and different...
This paper presents the design of high performance co-processor used to calculate the posterior probabilities for the embedded speech recognition of CHMM (Continuous Hidden Markov Model) with the MPIE (Maximum Probability Increase Estimation) algorithm to finish the most computation intensive operations in the speech recognition flow. The design of the co-processor is verified on Xilinx FPGA platform...
The use of reconfigurable hardware (HW) can improve the processing performance of many systems, including Wireless Sensor Networks (WSNs). Moreover, reconfigurable devices permit remote and runtime HW reconfiguration, which implies benefits in WSNs deployment and maintainability and, finally, cost reduction.
Partially reconfigurable hardware accelerators enable the offloading of computative intensive tasks from software to hardware at runtime. Beside handling the technical aspects, finding a proper reconfiguration point in time is of great importance for the overall system performance. Determination of a suitable point of reconfiguration demands the evaluation of performance degradation during runtime...
To investigate the on-sensor processing capabilities of FPGAs, this paper presents a bird call recognition system based on linear predictive cepstral coefficients (LPCC) and dynamic time warping (DTW) algorithms for sensor network applications, and compares two different implementations on a Xilinx Spartan-3E FPGA with MicroBlaze soft processor. The experimental results show that compared to the software-only...
Multimedia Systems on Chip have high computational requirements, as well as significant flexibility demands. Flexibility can be related with the reusability of the cores in charge of the execution of computation-intensive tasks, but also with the run-time adaptation of these cores to the execution of time-variable tasks, or to changing system conditions. Among the run-time flexibility requirements...
It's a promising way to improve performance significantly by adding reconfigurable processing unit to a general purpose processor. In this paper, a Reconfigurable Multi-Core (RMC) architecture combining general multi-core and reconfigurable logic is proposed. The Reconfigurable Logic is logically divided into Reconfigurable Processing Units (RPUs), which are coupled with General Purpose Cores (GPCs)...
Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology...
A mini VGA video capture and storage system is proposed, which can capture and convert the analog RGB video signals from VGA input port into 24-bit true-color digital image stream and store it into a mini-SD card in BMP file format. The power supply is one Lithium battery and can be recharged via USB port. The full control logic is realized inside one EP2C35 FPGA chip based on SoPC (System on a Programmable...
The discrete wavelet transform (DWT) and the embedded block coding with optimized truncation (EBCOT) account for most of the workload in JPEG2000 encoding. This paper presents a new hardware & software co-design that improves the JPEG2000 encoder's performance while keeping its flexibility by replacing the DWT and the EBCOT with hardware accelerators. In order to further improve the performance,...
Nowadays the real time video processing is becoming more and more critical. Thus the systems used for these purposes require powerful computation of the data in order to have short response time. Another attribute that is preferred for these systems to have, is versatility or offering the opportunity to be reconfigurable on demand. Co-design is a technique that involves both software and hardware...
This paper describes a design of a reconfigurable computing platform (RCP) based on the Intel Xeon general purpose processor and the Nallatech BenNUEY-PCI-4E field programmable gate array (FPGA) motherboard. The RCP is built to allow users with little or no knowledge of hardware design to program high performance computing applications that utilizes FPGA as the coprocessor. The RCP utilizes Impulse...
A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2n-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Exploiting the features of the MicroBlaze's integrated interfaces instructions are streamed on-demand to the coprocessor to keep the controlflow highly flexible. At the same time the dataflow...
Accelerators with little power consumption per computation performance are beginning to widely spread for High Performance Computing use, instead of general-purpose CPUs with much power consumption. They are GPUs, processors of Cell architecture, and FPGA accelerators. While these processors have much higher computation performance than general-purpose CPUs, they need specific programming environment...
Hardware/Software codesign of Elliptic Curve Cryptography has been extensively studied in recent years. However, most of these designs have focused on the computational aspect of the ECC hardware, and not on the system integration into a SoC architecture. We study the impact of the communication link between CPU and coprocessor hardware for a typical ECC design, and demonstrate that the SoC may become...
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