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This paper propose an efficient interconnect interface, which has been applied in reconfigurable multimedia system (REMUS). In order to achieve high performance of data share between multi cores, this interconnect interface applies overlapping operation mechanism in memory. Test of H.264 HiP (High Profile) decoding shows that the data exchange rate achieves a speedup of 285% compared with the AHB...
In this paper, a functional model of SystemC-based MPEG-2 decoder is presented, which is of heterogeneous multi-IP-cores and hybrid-interconnections. Considering the application-specific features into the design flow, three important aspects are analyzed, including function partition, parameter sharing, and interconnection topology, which are the key technical difficulties in the system level design...
We describe a design method to unify the IDCT and IQ operations for three popular video compression standards such as H.264 (up to high profile), MPEG-4 and VC-1. We use the concept of delta coefficient matrix to implement the unified IDCT circuit. Our circuit supports 4-point and 8-point IDCT's for H.264, MPEG-4 and VC-1. The unified IQ circuit uses a shared multiplier. The entire circuit was verified...
To deal with nowaday multi-standard audio and video processing, a heterogeneous multi-core SOC architecture is presented in this paper, which is composed of a general purpose RISC processor, an audio processing enhanced DSP and dedicated video processing accelerators. To exploit the task level concurrency among audio-video media decoding, an efficiency and flexible HW/SW cooperating architecture is...
AVS1-P2 is the newest video standard of Audio Video coding Standard (AVS) workgroup of China, which provides close performance to H.264/AVC main profile with lower complexity. In this paper, a platform independent software package is developed for AVS1-P2 decoder to facilitate embedded video codec development. In order to minimize the on-chip memory and save the time consumed in on-chip/off-chip data...
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