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Logic upset caused by contact discharge is studied using a test chip mounted on a board. Upset can be triggered by a parasitic NPN structure which couples the ESD protection to an N+ diffusion in the core circuitry. Upset often involves contention and thus is sensitive to transistor sizing.
In order to reduce minimum operating voltage (VDDmin) of CMOS logic circuits, a new method reducing the within-die random threshold (VTH) variation of transistors by a post-fabrication automatically selective charge injection using substrate hot electrons (SHE) is proposed along with novel circuitry to utilize this. In the new circuit, switches are added to combinational logic circuits in order to...
In this paper, we investigate optimum radiation hardened by design (RHBD) for use against single-event transients (SET) using low-pass filters (LPF) including RHBD techniques against single-event upsets (SEU) for sequential logic in 45 -nm technology in a terrestrial environment. Three types of LPF were investigated regarding their SET pulse immunities, area penalties, and performance penalties. We...
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