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Temperature variations caused by heat generation and dissipation can have significant performance implications on nanoscale CMOS logic circuits. In this paper, we show that such temperature-induced delay variations can be well controlled or even reduced by dynamically adjusting the voltage level of power supplies over a relatively small range. We thus propose a self-adaptive, temperature-aware voltage...
Ultralow-power subthreshold logic circuits are becoming prominent in embedded applications with limited energy budgets. Minimum energy consumption of digital logic circuits can be obtained by operating in the subthreshold regime. However, in this regime process variations can result in up to an order of magnitude variations in $I_{\mathrm{{\scriptscriptstyle ON}}}/I_{\mathrm{{\scriptscriptstyle OFF}}}$ ...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
Application of multiple-valued logic (MVL) in the design of digital devices opens additional opportunities. Multiple-valued logic also offers a possibility of increasing the functional complexity, implementing circuits that can perform comparable to the binary circuits. The main objective of this work is to design quaternary logic cells and with quaternary inputs and quaternary outputs. Logic Cells...
This paper shows the implementation and comparison of Carry Select Adder (CSA) using BEC (Binary Excess one Converter) and First Zero Finding (FZF) logic implementation techniques with optimization of the Full Adder (FA) cell by minimize number of transistors. The results have been analyzed and compared for implementation of both the above logic styles for 28T, 10T and 8T FA cells where as keeping...
In this paper, basically the delay and the noise margin parameter associated in the circuit has been analyzed. The paper gives a better approach for the reduction in delay variation and compares the result with different-different types of domino logic circuits. The other domino logic circuits used to discriminate the result of proposed circuit are footed domino logic circuit, footless domino logic...
In this paper, data-driven dynamic logic and its' variant split-path data-driven dynamic logic circuits are analyzed for dynamic and static power consumption. A new low-power methodology is introduced in order to reduce the leakage current while maintaining the speed advantages of the data driven dynamic logic. A sleep switch transistor is used in the data driven dynamic circuits in order to force...
Dynamic logic style is used in high performance circuit designs due to its high speed. But during cascading of dynamic gates, problem arises due to charge sharing, charge redistribution and charge leakage. To avoid these problems, domino logic design is used in the circuit due to their advantages such as their high speed and less noise immunity. In this paper we have proposed a new domino circuit...
The Reversible logic has emerged as more compatible and appropriate logic approaches and more prominent technology having its applications in the reversible operation based Low Power CMOS, Quantum Computing, Garbage inputs/outputs, Cryptography, Communication, nanotechnology, Optical Computing and Computer graphics. The Reversible logic circuit is very concise approach for the design of low power;...
Reversible logic has emerged as one of the most important approaches and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Garbage inputs/outputs, Cryptography, Communication, nanotechnology, Optical Computing and Computer graphics. This paper presents a novel reversible multiplexer gate is proposed and the design of differential reversible multiplexer using the...
Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides...
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