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A Huffman coding scheme with 3.9 compression ratio for the Large Hadron Collider experiment is proposed. A fully-synthesized scheme draws a small footprint layout of 60μm × 60μm in 65nm and 105μm × 105μm in 130nm CMOS process. The maximum operation frequencies are 435MHz for 65nm and 333MHz for 130nm, whereas the power consumption is 1.2mW and 1.9mW respectively. The resulting scheme enables a front-end...
This paper presents a 10 bit 90 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with an asynchronous conversion cycle control. The asynchronous operation allows the sampling rate to be swept over a wide range. The ADC doesn't require any external reference voltages and achieves an excellent performance without the need for calibration. The comparator uses an optimized...
Sigma-Delta Analog-to-Digital converter (ADC), is widely used in portable electronic products. An operational transconductance amplifier (OTA) is one of the most important components of this ADC. This paper reports a new design of low power fully differential OTA. In this design authors have used adaptive biasing technique and DC gain enhancement technique for improving design parameters as compared...
Analog to Information Converter (AIC) is the heart of an energy efficient bio potential acquisition system using compressed sensing (CS) technique. This paper presents the design and implementation of AIC. Charge redistribution Digital to Analog Convertors (DAC) is used for power and area efficiency. A successive approximation register (SAR) control logic and dynamic latch type comparator are used...
An 8-bit 2GS/s 250mW low power folding A/D converter(ADC) with a 45nm CMOS technology is described. In order to reduce the power consumption, a new folding block with a shut-down circuit is proposed. The role of shut-down circuit selectively cuts off the power supply of folding amplifiers, according to the input analog voltage. Further, an adaptive digital error correction technique is discussed to...
A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic design methodology to maximize the locking range over power consumption ratio is proposed. The test chip core area is only 25.6×24.8μm2 and measurements repeated over several samples demonstrate an operating frequency range from 25GHz to 102GHz with a maximum power consumption of 5.64mW from a 0.9V supply. The...
We propose a low-power and compact 25-Gb/s differential CMOS modulator driver. To achieve low power consumption, we employ an output driver with a high-gain single-stage amplifier and a gainless pre-driver with an equalizer function. In the pre-driver, we use area-efficient 3D inductors for the inductor peaking technique to obtain the equalizer function with compactness. We also employ a cascode amplifier...
A fully dynamic latched comparator has been designed to meet the requirement of high speed and low power consumption. Such comparators are used in high speed data converters. In this work, dynamic comparators are designed in two different technologies and compared on the basis of delay, offset voltage and power consumption. These comparators work on the concept of charge sharing. Main focus is given...
A low-voltage and low-power mixer using 0.18 μm CMOS technology is presented in this paper. The proposed mixer uses a weak inversion biasing technique in a source-driven topology. For high conversion gain, current reuse technique is applied to the input buffers. Moreover, the bulk-biased technique is used to achieve low supply voltage. The source-driven mixer exhibits a conversion gain of 8.68 dB,...
A simple circuit design technique for the realization of compact low-voltage low-power CMOS four-quadrant analog current multiplier circuit has been suggested. It is based on the use of the square-law characteristic in the NMOS current squaring function circuit operating in the saturation region. The suggested four-quadrant current multiplier circuit is designed for implementing in TSMC 0.25-μm CMOS...
High speed and low power transmission on optical interconnections can be achieved using ring-based optical modulators. 3D-integration of the ring modulator on top of the driver chip allows compact and cheap transmitters. 4-PAM modulation is considered for the first time for a high data rate.This paper presents a 10 Gb/s ring modulator driver with high and adjustable swing. The circuit is designed...
The increase in the use of electronic portable devices in the market has led to the use of the DC-DC converters. In different types of the DC-DC Converter the more efficient one to be chosen is the Buck converter. In the power electronics industry there are many types of voltage regulators and DC-DC Converters. But as concern with the VLSI Design logic the main aim is to reduce the area and the power...
A low-power hybrid analog-to-digital converter (ADC) architecture for high-speed medium-resolution applications is introduced. The architecture is a subranging time-interleaved ADC. In the first stage, a fast flash ADC resolves the three most significant bits. The remaining bits are generated by four time-interleaved low-power successive approximation register (SAR) ADCs, leading to 8-bit 1GS/s operation...
In this paper, an implementation of both interpolation and synchronization modules designed for RF receiver using power-gated ADC (PG-ADC) is presented. These modules allow lower bit error rates when demodulating non-uniformly sampled minimum-shift keying (MSK) signal. The proposed architectures are synthesized using CMOS 90 nm technology and are shown to have small occupied area (≈0.05 mm2) and low...
This paper introduces a new circuit technique for a discrete-time linear equalizer that can be used with current-integrating decision feedback equalizers. The DTLE samples and amplifies the input data in a clock phase then holds the output data in the other clock phase. The latter is the integrating phase of a current-integrating DFE. The DTLE is designed for a half-rate 8-Gbps serial-link receiver...
A compact 67 GHz LC oscillator implemented in 65nm bulk CMOS technology by STMicroelectronics is presented. It exploits a three-spiral transformer to achieve low phase noise and low power consumption. The measurements show that the oscillator core is capable to operate with a supply voltage as low as 0.6 V, while consuming 3.6 mW. The measured phase noise amounts to −96 dBc/Hz at 1 MHz offset from...
A modified structure of OTA in CMOS 65-nm with signal- and transient-current boosting is presented in this paper. The structure uses simple cascode current mirrors to overcome channel-modulation effect of the 65-nm MOSFETs and to maintain low-error current matching. Simulations show that the parasitic poles of the OTA in CMOS 65-nm are located at very high frequencies and the achievable bandwidth...
In this paper, we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power...
The remarkable evolution of human society over the centuries has been driven by information. As information became digitalized thanks to silicon technologies, creating, sharing, and searching of data have become much easier. Most recently, scaled silicon technology has been at the core of this information revolution, as it forms the basis on which digital devices, such as computers, smartphones, and...
This paper presents a low voltage, low leakage complementary metal oxide semiconductor current comparator using self-controlled voltage level technique. The self-controlled voltage level technique presents the integrated realization of an alternative method that is less intricate to implement. With the advancement in semiconductor technology, chip density and operating frequency are increasing, so...
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