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In this paper a 4-bit expandable algorithmic Analog-to-Digital Converter has been implemented. It is based on current mode technique. The Analog-to-Digital Converter has been implemented for 4-bits here but can be easily expanded for higher number of bits using the algorithm presented here. The converter uses a current comparator. We have simulated two popular structures of current comparators that...
This paper presents a design and implementation of a low noise phase-locked loop (PLL) based on ring oscillator to provide timing clocks for the analog-to-digital converter (ADC). The ring oscillator consists of four current control delay cells with current-steering amplifier (CSA) circuit. These fully switching differential delay cells are employed to reduce the phase noise of the ring oscillator...
This paper presents a fully integrated 9-11-GHz shock wave transmitter with an on-chip antenna and a digitally programmable delay circuit (DPDC) for pulse beam-formability in short-range microwave active imaging applications. The resistorless shock wave generator (SWG) produces a 0.4-V peak-to-peak (p-p) shock wave output in HSPICE simulation. The DPDC is designed to adjust delays of shock-wave outputs...
This paper proposes a new active shunt-peaked realization for MOS Current Mode Logic (MCML) based memory element. The circuit proposes the use of active inductors in shunt-peaking of MCML memory element. The technique of shunt-peaking offers a way of enhancing the performance of gates at high speed of operations. The benefit of the proposed circuit is verified by designing and simulating various MCML...
An all-digital de-skew clock generator for arbitrary wide range delay is proposed to minimize the instability of the clock settling while achieving fast locking time. The clock skew problem is detrimental in high-speed applications, especially when the skew is longer than multi-cycles. The proposed clock generator was fabricated in a 0.18-μm CMOS technology. The clock generator achieves a measured...
A multiloop method is presented for highly nonlinear ring oscillators in this paper. This circuit permits lower tuning gain through the use of coarse/fine frequency control, which also translates into a lower sensitivity to the voltage at the control lines. A 8-GHz VCO in SMIC 0.18μm 1P6M CMOS technology is designed. The linear tuning range of VCO is from 7.95 to 8.45GHz with the tuning voltage vary...
Windowed ADC is an attractive solution for the high efficiency digitally-controlled converters. However its limited conversion range restricts the transient speed for the dynamic voltage scaling applications. For slew rate improvement, this work designed a multi-mode PI/PID controller incorporated with the windowed ADC operation. In addition, to make output stable with no limit cycling, a current-controlled...
We have developed a novel timing vernier for a high integration CMOS timing generator of Automatic Test Equipment (ATE). To reduce area and power, the proposed timing vernier utilizes the charge injection architecture. An 893ps span, 7ps resolution timing vernier is fabricated in a 0.18 μm CMOS process. We achieved a linearity error of 4.2ps pp without calibration. The timing vernier occupies an area...
This paper deals with the implementation of full adder chains by mixing different CMOS full adder topologies. The proposed approach is based on cascading fast Gate Diffusion Input (GDI) Full Adders interrupted by static gate having driving capability, such as inverter, thus exploiting the intrinsic low power consumption of such topologies. The results obtained show that the proposed mixed-topology...
This paper proposes a time-to-digital converter (TDC) utilizing the cascaded time difference amplifier(TDA) and shows measurement results with 0.18um CMOS. The proposed TDC operates in two modes, a wide input range mode and a fine time resolution mode. We employ a non-linearity calibration technique based on lookup table. The wide input range mode shows 10.2ps time resolution over 1.3ns input range...
A 3.1-4.8GHz two-stage LNA for Group-1 UWB applications featuring current reuse, resistive feedback, complete and high ESD protection design is reported. ESD-RFIC co-design technique was used to ensure whole-chip optimization. The design is implemented in a foundry 0.18μm RFCMOS. Measurement shows a gain of 13.2dB/14.0dB, excellent input reflection of -13.4dB/-17.5dB, noise figure (NF) of 5.11dB/4...
In this paper, a fully integrated CMOS UWB transmitter for impulse system is presented, including a Gaussian pulse generator, a driver amplifier and a LC bandpass filter. In the pulse generator, a delay line with thermal insensitivity is used to generate the impulse with rising time independent of temperature. The transmitter is implemented in Chartered 0.18-μm RF CMOS technology. The experiment results...
A fast-lock all-digital register-controlled delay-locked loop (RCDLL) with wide-range duty cycle adjuster is presented. The architecture of the proposed fast-lock RCDLL uses the initial delay monitor without the delay line, which shares with the register controlled delay line for high accuracy of initial delay. Also, the duty cycle corrector of the DLL has achieved wide correction range to a small...
Hidden bombs and abandoned military landmines buried in the afterwar field has become a severe threat to the society. A stand-off, high sensitive and portable explosive detection system is required to help this situation. Nuclear Quadrupole Resonance (NQR) detection technology has proven to be a highly effective solution for unambiguously detecting explosives, since NQR is an inherent characteristic...
This paper presents the design and simulation of a ternary CMOS SRAM cell. A 16 × 16 ternary SRAM with ternary-compatible addressing was designed in a 0.18 μm process and the rise and fall delays were compared with a 16 × 16 binary SRAM. The ternary SRAM was created using cross-coupled ternary inverters. The inverters were optimized for high noise-margins and the optimum transistor sizings were presented...
A 9-11-GHz fully integrated shock wave generator using a 0.18-μm CMOS process for in-door active imaging applications is presented. This chip includes an on-chip wideband meandering dipole antenna, a shock wave generator and a 5-bit digitally programmable delay circuit. The pulse generator simulation produces a 0.4-V peak-peak (p-p) pulse amplitude with a 45.86-ps monopulse cycle in simulation. The...
The parameters of CMOS device will be affected by the variation of temperature and process variation. Due to these variations, a ring oscillator implemented in CMOS process will not have an constant output frequency which is designed in CAD tools. In order to get a constant frequency, additional circuit is needed to compensate the variation in both temperature and process. After investigate the drawback...
A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for IEEE standard WiMAX 802.16e. The FFT/IFFT processor is synthesized using UMC 0.18 μm CMOS technology and saves 33% area compared to a conventional implementation approach using radix-2 algorithm without sacrificing system throughput. Proposed Architecture also provides...
In this paper we present a novel 1-bit full adder cell. The cell offer less power consumption in comparison with the conventional and current implementation of the full adder cell, especially at low voltages. All transitions are used for simulation to obtain the delay and the power consumption parameters. Simulation is improved in term of power consumption. The new full adder cell is simulated at...
Quadrature oscillators are effective in applications such as clock-recovery circuits and complex signal processing. In this paper, the oscillation frequency of the CMOS inverter-type N-stage ring oscillator with wired-OR connections is analyzed. The analysis is applied to a quadrature oscillator proposed in 2008, called the ORIGAMI oscillator, and the extended N-stage ring oscillators. To verify the...
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