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A 10-b interpolation DAC is implemented for AMLCD column driver using 4b control of body potential via a built-in body buffer for interpolation in the buffer amplifier. Measured INL and DNL are 0.36 LSB and 0.35 LSB on 10b accuracy, respectively. Each channel of driver IC has a height of 295 μm, a pitch of 14 μm and a static current of 1 μA. The fabricated chip is...
A 2.4 GHz fully integrated Doherty power amplifier is fabricated in standard 90nm CMOS technology. The power amplifier employs a series combining transformer to eliminate bulky λ/4 transmission lines. An efficiency enhancement at power back-off is measured. The two-stage Doherty PA has 16.6 dB small-signal gain and produces 20.5 dBm saturated output power with a drain efficiency of 30.9% (PAE 26.7%)...
This paper presents a new receiver circuit that is suitable for low-swing interconnect schemes in CMOS nanometer technologies. Compared to the conventional receiver, which utilizes a PMOS feedback transistor, the proposed configuration is based on an auxiliary cross-coupled structure, which provides significant reduction of the delay time and eliminates the short circuit current, during transitions...
The goal of this paper is to reduce the power and area of the Static Random Access Memory (SRAM) array while maintaining the competitive performance. Here the various configuration of SRAM array is designed using both the six-transistor (6T) SRAM cell and a new loadless four-transistor (4T) SRAM cell in deep submicron (130nm, 90nm and 65nm) CMOS technologies. Then it is simulated using HSPICE to check...
In this paper we present an ultra low-voltage pseudo differential pair based on a clocked semi floating-gate transistor. The clocked semi floating-gate transistors are exploited to increase the current level for ultra low supply voltages and may be used in ultra low voltage mixed signal design. The pseudo differential pair may operate at supply voltages down to 250 mV. Simulated data for 90 nm CMOS...
A new output buffer with low switching noise and load adaptability is designed based on a TSMC 90 nm CMOS technology. The proposed buffer can reduce switching noise induced on supply lines and output ringing while achieving very fast output transitions. Moreover, the load adaptive method is simple and effective. Simulation results demonstrate that the proposed buffer achieves 4.1%-53.5% improvements...
This paper describes a design and implementation methodology for fine-grain power gating. Since sleep-in and wakeup are controlled in a fine granularity in run time, shortening the transition time between the sleep and active states is strongly required. In particular, shortening the wakeup time is essential because it affects the execution time and hence does the performance. However, this requirement...
This paper presents the design of novel LVDS (Low-Voltage-Differential-Signaling) output buffer for Gb/sper-pin operation using 90 nm CMOS technology. The proposed LVDS driver is designed to reduce chip area, using a novel bipolar transistor switch. The proposed LVDS transmitter is operated at 1.8 V low-power supply. Its maximum data rate is 2.8 Gb/s approximately. Also, the new structural ESD (Electro-Static...
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