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Recently, high-resolution TDCs have gained more and more popularity due to their increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight measurement units. Similar to ADCs, existing architectures of TDCs can be divided into several categories: flash TDCs, pipeline TDCs, and SAR TDCs. The highest achievable time resolution of a TDC is mainly limited by the CMOS gate delay...
A 0.18 μm CMOS digitally controlled DC-DC buck converter is presented. An all-digital 8 b frequency-domain ΔΣ ADC is used for the feedback path, and a 9 b segmented digital PWM is used for power stage control. A regulated output voltage accuracy of 1% and maximum efficiency of 94% is achieved with less than 14 mVpp ripple and a settling time of 100 μs for a 300 mA load transient.
The paper describes a four-order delta-sigma modulation (DSM) with 15 levels quantizer which is used in a 24-bit 44.1-kHz sample-rate audio digital-to-analog converter (DAC). An odd level quantizer has been chosen instead of an even level to reduce quantization noise. The noise transfer function (NTF) is designed to have the zeros optimally in order to increase DR. The peak SNR of the DSM is about...
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