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A process-insensitive current-controlled delay generator is presented with a large tunable range of the time delay. By adopting process variation compensation techniques in the generation of time delay, the delay generator is able to provide process-insensitive clock pulses. The circuit has been fabricated in 90 nm CMOS technology, consumes 310 μW from a 1.1V supply. Using, in a typical...
A fractional-N digital PLL with spread-spectrum capability occupies 190??200 ??m2 in 65 nm CMOS. It features a 190-to-4270 MHz digitally controlled ring oscillator and does not use any TDC. The period jitter is 1.4 psrms (15 pspp) at 3 GHz and 8.4 psrms (75 pspp) at 375 MHz. The PLL dissipates 1.85 mW plus 3.3 mW/GHz from 1.3 V and 1.1 V dual supplies.
Quadrature oscillators are effective for clock recovery circuits, complex signal processing, etc. In this report, two new quadrature oscillator circuits based on tetrahedral oscillators are proposed. The proposed quadrature oscillators are simulated and tested by the breadboard circuit in order to verify their electrical performances.
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13-mum CMOS process. For input frequency of 25 MHz, the measured jitter is 2.46 ps (rms) and plusmn9.33 ps (pk-pk) at 200-MHz output frequency, while achievable maximum static...
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