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Gated resistor is an accumulation mode device without any junction (p-n junction or Schottky junction) in which the channel doping concentration is generally equal to doping concentration on the source and drain. Gated resistors have been fabricated to avoid the super steep and troublesome doping profile of conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It simplifies the...
We report on the thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO2 and HfO2 gate dielectrics. The source-drain leakage current is suppressed by the introduction of intrinsic regions adjacent to the drain side, reducing the electric field at the tunnel junction. We also investigate the temperature dependence of the TFET characteristics, as well as the low frequency...
In this paper, we report the possibility of achieving sub-kT/q subthreshold slope (i.e. lower than 59.6 mV/decade at T=300 K) without using either impact ionization or band-to-band tunneling. The device uses intraband tunneling within the conduction band through barriers whose shape varies with the applied gate voltage. Subthreshold slope as low as 56.5 mV/decade is reported at T=300 K. The VBT reported...
Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature...
We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET),...
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