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Based on the 2011 ITRS road map, the greater accessibility of higher number of TSVs in a specified area depends on the smarter miniaturization of the interconnect dimension in 3D IC packaging. Scaling down the TSV dimension has an inevitable effect on resistance, capacitance, signal transmission as well as the thermo-mechanical stress. We report that the lowering of the TSV diameter is permissible...
The convergence and miniaturization of the consumer electronic products such as cell phones and digital cameras has led to the vertical integration of packages i.e., 3-D packaging. 3-D chip stacking is emerging as a powerful tool that satisfies such Integrated Circuit (IC) package requirements. 3-D technology is the trend for future electronics, especially hand-held, hence, making it an important...
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