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A simple method is described to protect polycrystalline silicon (polysilicon) from electrochemical corrosion which often happens when the Micro-Electro-Mechanical systems (MEMS) device is released in HF-based solutions, especially when the device contains noble metal. We propose to employ a photoresist (PR) layer to cover the noble metal layer, which electrically contacts with the underlying polysilicon...
A new fabrication process, which includes deposition of thin silver film on silicon surface prior to wet etching, is proposed for realizing aligned silicon nanowires with high uniformity, resulting in black nonreflecting silicon surface.
A topography simulation of BiCS memory hole etching is performed. The model parameters are fitted by elementary experiments of Si and SiO2 etching, and BiCS topography simulation is performed without parameter fitting. Our new model describes the experimental topography of BiCS memory hole, including taper angles and undercuts of stacked films. The point of the modeling is that it takes into consideration...
SLIM-Cut method [1] addresses one of the most important challenges of crystalline-Si for photovoltaics: kerf-free watering of substrates as thin as 50 microns. The SLIM-Cut technology is fully based on mechanical stress and it is compatible with low-cost fabrication methods: a stress field is applied to a silicon wafer so that a crack propagates in the silicon substrate parallel to the surface at...
Silicon rich oxide has shown photoemission. However, normally it is required a high temperature annealing in order to get intense emission. On the other hand, Si nanocrystals, nC, obtained by electrochemical methods and poured in a solutions have shown photoemission that depends on their size. Then, Si nC obtained by electrochemical methods are an alternative to obtain emissive silicon rich oxide...
We discuss aspects of low temperature processing relating to the formation of through-silicon vias [TSV] for 3D-IC applications. An optimized deep silicon etch process produces 10:1 aspect ratio vias with scallop size less than 50 nm and with minimal bow and sidewall roughness. Emphasis is given to a low temperature [ges150degC] PECVD dielectric liner deposition process which produces stable, low...
We improve the performance of thin-film solar cells using polycrystalline silicon (poly-Si) films formed by flash lamp annealing (FLA) of precursor amorphous Si (a-Si) films on glass substrates by modulating their surface structures. The surface morphology of the poly-Si films can be easily controlled by conventional wet chemical etching using mixed acid of HF and HNO3, accompanied by effective reduction...
In this paper, the via-last TSV process using dry film lithography will be presented. Historically we used dry film resist (DFR) for the copper rerouting (via metallization) step only, but here we also tried implementing it for via etching. In the first part of the paper the via-last process flow will be briefly described. Then the copper rerouting lithography using dry film will be presented. This...
The composite structure of silicon tips and vertical aligned carbon nanotubes (CNTs) was prepared using plasma enhanced hot filament chemical vapor deposition (PE-HFCVD) method on the silicon wafer, and Au/Ni film coated on the substrate was considered as a catalyst. High proportion hydrogen of 96% volume percentage and high total pressure are used during preparing process, and the pure CNTs, pure...
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