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In this paper, we introduce an impedance-matched bidirectional multidrop (IMBM) DQ bus, together with a 4.8-Gb/s transceiver for a memory controller that supports this bus. Reflective ISI is eliminated at each stub of the IMBM DQ bus by resistive unidirectional impedance matching. A prototype memory controller transceiver is designed and fabricated in a 0.13- CMOS process and operates with...
This paper describes a new topology and implementation of a 10 Gbps voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the low power driver achieves the proper internal chip impedance required for matching the line impedance. As a result, return loss is minimized and good signal integrity is achieved. The driver, which consists of a...
This paper describes a new topology and implementation of a 10 Gbps LVDS (low voltage differential signaling) voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the driver achieves ultra low power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
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