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Bilateral filtering (BLF) and median filtering (MF) are key components in many applications. As the image resolution grows rapidly, implementation of efficient filtering is highly demanded. In this paper, we present a unified VLSI architecture that is able to compute both kinds of filters for 4k2k videos at 30fps. One feature of this design is that we leverage an emerging layer-based algorithm for...
This paper presents a new alternative for design of modern hi-resolution remote sensing devices for application in consumer products. Near-field radars may perform security, bio or gesture detection tasks. New approach is especially introduced in prototype of system-on-chip (SoC) radar used as smart motion sensor embedded in TV set. Moreover, we focused mainly on critical issues of design: integration...
Modern GPGPUs employ thousands of threads for parallel execution. The massive threads often compete in the small sized first level data (L1D) cache, which leads to severe cache thrashing problem and hurts the GPGPU performance. In this paper, we apply victim cache design into GPGPUs to alleviate L1D cache thrashing problem for better data locality and system performance. Instead of a small fully associative...
This paper discusses the design of an experimentation platform intended for prototyping low-cost neural networks for on-chip integration, towards supporting built-in self-test, post-production self-calibration, and trust evaluation capabilities. Particular emphasis is given to cost-efficient implementation reflected in stringent area and power constraints of circuits dedicated to neural networks,...
This paper presents the system-level modeling of a Reconfigurable System on Chip (RSoC) that is being currently developed in our institution. Although there is a wide range of possible applications, our system is initially aiming fruit monitoring system. The proposed RSoC contains a 32-bit RISC microprocessor, reconfigurable structures, analog and digital interfaces, an RF transceiver and an Active...
“What is PSoC” is an application related review of programmable array systems, the system-on-chip, or PSoC. The hardware and system requirements are explained, hand to hand with practical notes. Description of two examples of embedded wireless systems with digital data modulation follows the theory.
This paper presents the development and test of the standard IEC-60870-5 application layer protocol for a Remote Terminal Unit (RTU) based on open hardware and software. The RTU hardware is an embedded system, a SoC-type design using FPGA that has been programmed with the open core LEON with Linux operating system running over it, so both the hardware and IOS are open source. For prototyping the GR-XC3S-1500...
An important share of the consumer electronics market is focused on devices capable of running multimedia applications, like audio and video decoders. In order to achieve the performance level demanded by these applications, it is important to develop specialized hardware IPs in order to cope with the most computational intensive parts. Nowadays, designers are facing the challenge of integrating several...
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