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Regular expression pattern matching circuits have been implemented based on NFA. Most of them adapted the one-hot state encoding. Recently FPGAs with 6-input lookup tables (6-LUTs) such as Virtex-5 has been announced. However, if regular expression matching circuits are implemented using one-hot encoding on FPGAs with 6-LUTs, additional inputs of 6-LUTs may be wasteful. In this paper, we propose a...
We propose a built-in scheme for generating all patterns of a given deterministic test set T. The scheme is based on grouping the columns of T, so that in each group of columns the number ri of unique representatives (row subvectors) as well as their product R over all such groups is kept at a minimum. The representatives of each group (segment) are then generated by a small finite state machine (FSM)...
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